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Radio frequency data communications device

  • US 6,696,879 B1
  • Filed: 11/22/2000
  • Issued: 02/24/2004
  • Est. Priority Date: 05/13/1996
  • Status: Expired due to Fees
First Claim
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1. A frequency doubler comprising:

  • a first cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair and a first one of the transistors of the second pair having gates coupled together, a second one of the transistors of the first pair and a second one of the transistors of the second pair having gates coupled together, the first transistor of the first pair and the second transistor of the second pair having drains coupled together, the second transistor of the first pair and the first transistor of the second pair having drains coupled together, the first cell further including a third pair including first and second transistors having sources coupled together, the first transistor of the third pair having a drain coupled to the source of the second transistor of the first pair, the second transistor of the third pair having a drain coupled to the source of the second transistor of the second pair, and the first cell further including a current source coupled to the sources of the third pair and forward biasing the third pair; and

    a second cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair of the second cell and a first one of the transistors of the second pair of the second cell having gates coupled together, a second one of the transistors of the first pair of the second cell and a second one of the transistors of the second pair of the second cell having gates coupled together, the first transistor of the first pair of the second cell and the second transistor of the second pair of the second cell having drains coupled together, the second transistor of the first pair of the second cell and the first transistor of the second pair of the second cell having drains coupled together, the second cell further including a third pair including first and second transistors having sources coupled together, the first transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the first pair of the second cell, the second transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the second pair of the second cell, and the second cell further including a current source coupled to the sources of the third pair of the second cell and forward biasing the third pair of the second cell, the second transistor of the third pair of the second cell having a gate defining a third input node of the second cell, and the first transistor of the third pair of the second cell having a gate defining a fourth input node of the second cell; and

    the drain of the second transistor of the first pair of the second cell being coupled to the drain of the second transistor of the first pair of the first cell, the drain of the second transistor of the second pair of the second cell being coupled to the drain of the second transistor of the second pair of the first cell;

    wherein the first cell is configured to receive a first sinusoidal wave, wherein the second cell is configured to receive a sinusoidal wave shifted from the first sinusoidal wave, and wherein no integrator is employed in the frequency doubler.

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