Rendering pipeline

• US 6,697,063 B1
• Filed: 11/25/1997
• Issued: 02/24/2004
• Est. Priority Date: 01/03/1997
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA US Investment Company (NVIDIA Corporation)
• Inventors: Zhu, Ming Benjamin
• Primary Examiner(s): Jankus, Almis R.
• Application Number:
  US08/978,491
• Time in Patent Office: 2,282 Days
• Field of Search: 345/423, 345/421, 345/422
• US Class Current: 345/421
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

A rendering pipeline system for a computer environment uses screen space tiling (SST) to eliminate the memory bandwidth bottleneck due to frame buffer access and performs screen space tiling efficiently, while avoiding the breaking up of primitives. The system also reduces the buffering size required by SST. High quality, full-scene anti-aliasing is easily achieved because only the on-chip multi-sample memory corresponding to a single tile of the screen is needed. The invention uses a double-z scheme that decouples the scan conversion/depth-buffer processing from the more general rasterization and shading processing through a scan/z engine. The scan/z engine externally appears as a fragment generator but internally resolves visibility and allows the rest of the rendering pipeline to perform setup for only visible primitives and shade only visible fragments. The resulting reduced raster/shading requirements can lead to reduced hardware costs because one can process all parameters with generic parameter computing units instead of with dedicated parameter computing units. The invention processes both opaque and transparent geometries.

Claims

1. A method of determining visibility for a plurality of fragments comprising:

performing a first rendering function to determine visibility information from a first plurality of geometries, the first rendering function comprising;

receiving the first plurality of geometries including a plurality of vertices and vertices connectivity information, each vertex including x, y, and z coordinates;

determining z values for each x and y location in a screen space for each geometry in the first plurality of geometries;

comparing z values for each geometry in the first plurality of geometries at each x and y location; and

storing a z value for each x and y location; and

performing a second rendering function to determine which of a second plurality of geometries are to be shaded, the second rendering function comprising;

receiving the second plurality of geometries including a plurality of vertices and vertices connectivity information, each vertex including x, y, and z coordinates;

determining z values for each x and y location in a screen space for each geometry it the second plurality of geometries; and

comparing the determined z values to the stored z value at each x and y location,

wherein the second plurality of geometries includes each of the first plurality of geometries and at least one additional geometry.

2. The method of claim 1 further comprising:

output a fragment if its determined z value is less than or equal to the corresponding stored z value.

3. The method of claim 1 further comprising:

outputting a fragment if its determined z value is greater than or equal to the corresponding stored z value.

4. The method of claim 1 further comprising:

outputting a geometry and a corresponding coverage mask if at least one determined z value for the geometry is less than or equal to the corresponding stored z value.

5. The method of claim 1 further comprising:

outputting a geometry and a corresponding coverage mask if at least one determined z value for the geometry is greater than or equal to the corresponding stored z value.

6. The method of claim 1 wherein the first plurality of geometries is selected from the second plurality of geometries at random.

7. An integrated circuit including a graphics pipeline comprising:

a memory interface configured to receive screen x, y, and z coordinates from a first plurality of memory locations and surface parameters from a second plurality of memory locations;

a scan/z engine configured to receive the screen x, y, and z coordinates from the memory interface without receiving other surface parameters, the scan/z engine further configured to determine visibility information; and

a rasterizer coupled to the scan/z engine and configured to receive the surface parameters from the memory interface.

8. The integrated circuit of claim 7 wherein the surface parameters comprise parameters other than x, y, and z coordinates.

9. The integrated circuit of claim 7 wherein the x, y, and z coordinates comprise a portion of a screen x, y, and z stream, and the screen x, y, and z steam further includes mode information related to scan conversion and depth operations.

10. The intergrated circuit of claim 9 wherein screen x, y, and z coordinates are added to the visibility information determined by the scan/z engine.

11. A personal computer comprising:

a processor; and

a graphics card coupled to the processor, the graphics card comprising;

a memory; and

the integrated circuit of claim 7 coupled to the memory.

12. A game console comprising:

a processor; and

a graphics card coupled to the processor, the graphics card comprising;

a memory; and

the integrated circuit of claim 7 coupled to the memory.

13. A method of rendering geometries comprising:

performing a first rendering function comprising;

receiving a plurality of geometries including a plurality of vertices and vertices connectivity information, each vertex including x, y, and z coordinates;

determining z values for each x and y location in a screen space for each geometry in the plurality of geometries;

comparing z values for each geometry in the plurality of geometries at each x and y location; and

storing a z value for each x and y location;

performing a second rendering function comprising;

receiving the plurality of geometries;

determining z values for each x and y location in a screen space for each geometry in the plurality of geometries; and

comparing the determined z values to the stored z value at each x and y location; and

output a fragment if any subsample of the fragment is determined to be visible,

wherein the fragment comprises a fragment coverage.

14. The method of claim 13 wherein the fragment is output to a rasterizer.

15. The method of claim 14 wherein the rasterizer receives the fragment comprising multiple samples and generates one color sample.

16. The method of claim 13 wherein the method is executed by an integrated circuit.

17. The method of claim 13 wherein the method is executed by an integrated circuit, the integrated circuit is coupled to a memory, and

wherein the integrated circuit and memory are included on a graphics card housed in a personal computer.

18. A method of determining visibility for a plurality of fragments comprising:

performing a first rendering function comprising;

receiving a plurality of geometries including a plurality of vertices and vertices connectivity information, each vertex including x, y, and z coordinates;

determining z values for each x and y location in a screen space for each geometry in the plurality of geometries;

comparing z values for each geometry in the plurality of geometries at each x and y location; and

storing a z value for each x and y location;

performing a second rendering function comprising;

receiving the plurality of geometries;

determining z values for each x and y location in a screen space for each geometry in the plurality of geometries; and

comparing the determined z values to the stored z value at each x and y location;

outputting a plurality of fragments, wherein each fragment comprises a fragment coverage; and

merging two fragments to form a merged fragment, wherein the merged fragment comprises a merged fragment coverage.

19. The method of claim 18 wherein the two fragments are merged according to an alpha value.

20. The method of claim 18 wherein the method is executed by an integrated circuit.

21. An integrated circuit including a rendering pipeline comprising:

a screen space tiler;

a memory interface coupled to the screen space tiler;

a scan/z engine coupled to the memory interface;

a rasterizer coupled to the memory interface; and

a shader coupled to the rasterizer.

22. The integrated circuit of claim 21 further comprising a first-in first-out memory coupled between the scan/z engine and the rasterizer.

23. The integrated circuit of claim 21 wherein the memory is configured to receive screen x, y, and z coordinates from a first portion of a memory and to provide the screen x, y, and z coordinates to the scan/z engine, and the memory interface is further configured to receive surface parameters from a second portion of the memory and to provide the surface parameters to the rasterizer.

24. The integrated circuit of claim 23 wherein the surface parameters comprise parameters other than x, y, and z coordinates.

25. The integrated circuit of claim 23 wherein the memory interface is further configured to access a third portion of the memory as a first-in first-out memory coupled between the scan/z engine and the rasterizer.

26. The integrated circuit of claim 25 wherein the memory interface is further configured to receive textures from a fourth portion of the memory and to provide the textures to the shader.

27. The integrated circuit of claim 26 wherein the shader is coupled to a blender.

28. A personal computer comprising:

a processor; and

a graphics card coupled to the processor, the graphics card comprising;

a memory; and

the integrated circuit of claim 21 coupled to the memory.

29. A game console comprising:

a processor; and

a graphics card coupled to the processor, the graphics card comprising;

a memory; and

the integrated circuit of claim 21 coupled to the memory.