Fast frame readout architecture for array sensors with integrated correlated double sampling system

• US 6,697,108 B1
• Filed: 12/30/1998
• Issued: 02/24/2004
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dierschke, Eugene G., Chen, Zhiliang Julian
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): WHIPKEY, JASON T
• Application Number:
  US09/223,166
• Time in Patent Office: 1,882 Days
• Field of Search: 348/241, 348/243, 348/308
• US Class Current: 348/241
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise

Abstract

A MOS architecture for reading rows of pixels in an area array imager. After initial setup, individual pixels are read one row at a time using one clock pulse per pixel.

Claims

1. An integrated imaging chip, comprising:

a plurality of pixel circuits in an m row by n column array, said pixel circuits each comprising

a photosensitive element coupled between a first node and one side of a power source,

a first switch coupled between said first node and another side of said power source, and

a first MOS transistor coupled by a source and a drain between said other side of said power source and one port of a second switch, a gate of said MOS transistor being connected to said first node, another port of said second switch being coupled to an output of the pixel circuit;

a plurality of column readout circuits, each operatively connected to receive at an input pixel signals from said outputs of said pixel circuits of at least one respective column of said pixel circuits, said column readout circuits each comprising

a first current source coupled between said input of said column readout circuit and said one side of said power source,

a second MOS transistor,

a first capacitor coupled between said input of said column readout circuit and a gate of said second MOS transistor,

a third switch coupled between said gate of said second MOS transistor and said one side of said power source,

a second current source coupled between said other side of said power source and a second node, said second MOS transistor being coupled by a source and a drain between said second node and said one side of said power source, and

a second capacitor having a port coupled between said second node and one port of a fourth switch, another port of said fourth switch being coupled to an output port of said column readout circuit; and

an output circuit operatively connected to receive at an input data signals from said outputs of each of said column readout circuits, said output circuit comprising

a third MOS transistor coupled by a source and a drain between said one side of said power source and an output node of said output circuit, and having a gate coupled to said input of said output circuit,

a third current source couDled between said other side of said power source and said output node of said output circuit, and

a fifth switch coupled between said gate of said third MOS transistor and said one side of said power source;

wherein said column readout circuits are thereby collectively configured to all perform, in parallel, sequentially correlated double sampling operations on pixel readout data, and then in succession, to serially provide respective analog outputs to said output circuit.

2. The integrated circuit of claim 1, wherein said array comprises row and column select circuits comprising one-hot encoded flip-flops.

3. The integrated circuit of claim 1, wherein a row reset circuit comprises one-hot encoded flip-flops.

4. The integrated circuit of claim 1, wherein after said pixel circuits are prepared for readout, successive pixels of a row are read out with clock signals in a one-to-one relationship.

5. An imaging system, comprising:

a focusing element;

an integrated MOS imaging chip for receiving images from said focusing element, and comprising;

a plurality of pixel circuits in an m row by n column array, said pixel circuits each comprising

a photosensitive element coupled between a first node and one side of a power source,

a first switch coupled between said first node and another side of said power source, and

a first MOS transistor coupled by a source and a drain between said other side of said power source and one port of a second switch, a gate of said MOS transistor being connected to said first node, another sort of said second switch being coupled to an output of the pixel circuit;

a plurality of row select circuits operatively connected to each of said pixel circuits;

wherein said row select circuit provides at least a first row command to said second switch of said pixel circuits;

wherein ones of said row select circuit are operatively connected to ones of said pixel circuits;

a plurality of row reset circuits;

wherein ones of said row reset circuit are operatively connected to ones of said pixel circuits to provide a reset command to operate said first switch;

a plurality of column readout circuits operatively connected to receive signals from said pixel circuits;

wherein each of said column readout circuits are operatively connected to receive signals from a column of pixel circuits and to perform sequentially correlated double sampling operations on pixel readout data, said column readout circuits each comprising

a first current source coupled between said input of said column readout circuit and said one side of said power source,

a second MOS transistor,

a first capacitor coupled between said input of said column readout circuit and a gate of said second MOS transistor,

a third switch coupled between said sate of said second MOS transistor and said one side of said power source,

a second current source coupled between said other side of said power source and a second node, said second MOS transistor being coupled by a source and a drain between said second node and said one side of said power source, and

a second capacitor having a port coupled between said second node and one port of a fourth switch, another port of said fourth switch being coupled to an output port of said column readout circuit;

a plurality of column control circuits;

wherein ones of said column control circuits are operatively connected to ones of said column readout circuits; and

an output circuit operatively connected to receive data signals from each of said column readout circuits;

wherein successive pixels of a row are read out by successive clock signals in a one-to-one relationship;

a microprocessor for processing images from said imaging chip; and

a storage medium for storing said processed images.

6. The system of claim 5, wherein said row and column select circuits comprise one-hot encoded flip-flops.

7. The system of claim 6, wherein said row reset circuit comprises one-hot encoded flip-flops.