Level shift circuit

• US 6,703,863 B2
• Filed: 01/07/2003
• Issued: 03/09/2004
• Est. Priority Date: 01/15/2002
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Gion, Masahiro
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Linh Van
• Application Number:
  US10/337,429
• Publication Number:
  US 20030132778A1
• Time in Patent Office: 427 Days
• Field of Search: 326/62-89, 326/110, 326/58, 326/27, 327/534, 327/535
• US Class Current: 326/62
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

In a level shift circuit according to the invention, either an input signal IN or an inverted input signal XIN, which are input into the gate electrodes of n-type transistors for signal input, is also given to the substrate of that n-type transistor via p-type transistors for substrate bias. When the signal IN or XIN rises and changes, the threshold voltages of the n-type transistors for signal input is lowered due to the substrate bias effect. Consequently, even if the signal IN or XIN has a low voltage level, operation is carried out at high speeds. Also, when either an output signal OUT or an inverted output signal XOUT is changed to a high voltage level, the transistors for substrate bias become non-conducting, and thus the input signal IN or the inverted input signal XIN is not supplied to the substrate of the n-type transistors for signal input other than when the signal is changing. Consequently, a constant passing-through current does not flow to the substrate of these transistors.

Claims

1. A level shift circuit, into which an input signal and an inverted input signal are input, which shifts an amplitude level of the input signal and the inverted input signal to an amplitude level that is higher than that amplitude level, and which outputs at least one of an output signal and an inverted output signal having the amplitude level after shifting, the level shift circuit comprising:

a first n-type transistor for signal input, into whose gate electrode the input signal is input;

a second n-type transistor for signal input, into whose gate electrode the inverted input signal is input;

a first p-type transistor for substrate bias, into whose source electrode the input signal is input, whose drain electrode is connected to a substrate of the first n-type transistor for signal input, and into whose gate electrode the output signal is input; and

a second p-type transistor for substrate bias, into whose source electrode the inverted input signal is input, whose drain electrode is connected to a substrate of the second n-type transistor for signal input, and into whose gate electrode the inverted output signal is input.

2. The level shift circuit according to claim 1, further comprising:

a first n-type transistor for resetting, whose source electrode is connected to a low voltage power source, whose drain electrode is connected to the substrate of the first n-type transistor for signal input, and into whose gate electrode the output signal is input; and

a second n-type transistor for resetting, whose source electrode is connected to the low voltage power source, whose drain electrode is connected to the substrate of the second n-type transistor for signal input, and into whose gate electrode the inverted output signal is input.

3. The level shift circuit according to claim 2, further comprising:

a first delay element connected to the gate electrode of the first n-type transistor for resetting, and which is for delaying input of the output signal to that gate electrode; and

a second delay element connected to the gate electrode of the second n-type transistor for resetting, and which is for delaying input of the inverted output signal to that gate electrode.

4. The level shift circuit according to any of claims 1 to 3, wherein the inverted output signal and the output signal are input into the drain electrodes of the first and the second n-type transistors for signal input, respectively, the level shift circuit further comprising:

a p-type transistor for blocking, which is arranged on a route connecting a high voltage power source to the drain electrodes of the first and the second n-type transistors for signal input, into whose gate electrode a control signal is input, and which becomes non-conducting when a power source of a circuit that outputs the input signal and the inverted input signal is shut down; and

first and second n-type transistors for shutdown, arranged between the drain electrodes of the first and the second n-type transistors for signal input and the low voltage power source, respectively, into whose gate electrodes the control signal is input, and which become conducting during the shut down.

5. The level shift circuit according to any of claims 1 to 3, wherein at least the first and the second n-type transistors for signal input are formed on an insulating substrate.

6. The level shift circuit according to any of claims 1 to 3, wherein a signal line is connected to the drain electrode of at least one of the first and the second n-type transistors for signal input, and through the signal line, only one of the output signal and the inverted output signal is output.

7. A level shift circuit, into which an input signal and an inverted input signal are input, which shifts an amplitude level of the input signal and the inverted input signal to an amplitude level that is higher than that amplitude level, and which outputs at least one of an output signal and an inverted output signal having the amplitude level after shifting, the level shift circuit comprising:

a first n-type transistor for signal input, into whose gate electrode the input signal is input;

a second n-type transistor for signal input, into whose gate electrode the inverted input signal is input;

a first n-type transistor for substrate bias, into whose source electrode the input signal is input, whose drain electrode is connected to a substrate of the first n-type transistor for signal input, and into whose gate electrode the inverted output signal is input; and

a second n-type transistor for substrate bias, into whose source electrode the inverted input signal is input, whose drain electrode is connected to a substrate of the second n-type transistor for signal input, and into whose gate electrode the output signal is input.

8. The level shift circuit according to claim 7, further comprising:

a first n-type transistor for resetting, whose source electrode is connected to a low voltage power source, whose drain electrode is connected to the substrate of the first n-type transistor for signal input, and into whose gate electrode the output signal is input; and

a second n-type transistor for resetting, whose source electrode is connected to the low voltage power source, whose drain electrode is connected to the substrate of the second n-type transistor for signal input, and into whose gate electrode the inverted output signal is input.

9. The level shift circuit according to claim 8, further comprising:

a first delay element connected to the gate electrode of the first n-type transistor for resetting, and which is for delaying input of the output signal to that gate electrode; and

a second delay element connected to the gate electrode of the second n-type transistor for resetting, and which is for delaying input of the inverted output signal to that gate electrode.

10. The level shift circuit according to any of claims 7 to 9, wherein the inverted output signal and the output signal are input into the drain electrodes of the first and the second n-type transistors for signal input, respectively, the level shift circuit further comprising:

a p-type transistor for blocking, which is arranged on a route connecting a high voltage power source to the drain electrodes of the first and the second n-type transistors for signal input, into whose gate electrode a control signal is input and which becomes non-conducting when a power source of a circuit that outputs the input signal and the inverted input signal is shut down; and

first and second n-type transistors for shutdown, arranged between the drain electrodes of the first and the second n-type transistors for signal input and the low voltage power source, respectively, into whose gate electrodes the control signal is input, and which become conducting during the shut down.

11. The level shift circuit according to any of claims 7 to 9, wherein at least the first and the second n-type transistors for signal input are formed on an insulating substrate.

12. The level shift circuit according to any of claims 7 to 9, wherein a signal line is connected to the drain electrode of at least one of the first and the second n-type transistors for signal input, and through the signal line, only one of the output signal and the inverted output signal is output.