Method of manufacturing a transistor

• US 6,706,615 B2
• Filed: 03/31/2003
• Issued: 03/16/2004
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Shindengen Electric Manufacturing Company Limited
• Original Assignee: Shindengen Electric Manufacturing Company Limited
• Inventors: Takemori, Toshiyuki, Kunori, Shinji, Kitada, Mizue
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Lindsay, Jr., Walter L.
• Application Number:
  US10/401,672
• Publication Number:
  US 20030203576A1
• Time in Patent Office: 351 Days
• Field of Search: 438/430, 438/404, 438/405, 438/243, 438/129, 438/128, 438/268, 438/406
• US Class Current: 438/430
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.

Claims

1. A method of manufacturing a transistor having a semiconductor substrate having a drain layer of a first conductivity type and an opposite conductive region of a second conductivity type in contact with the drain layer;

comprising steps of;

forming a deep trench reaching from a surface of the opposite conductive region to the drain layer in the semiconductor substrate, wherein a bottom of deep trench is positioned in the drain layer;

disposing a semiconductor filler of the second conductivity type on a bottom of the deep trench, wherein top of the semiconductor filler is deeper than a bottom of the opposite conductive region;

forming a gate insulating film on an inner side surface of a gate trench composed of an upper part than the top of semiconductor filler in the deep trench;

forming a gate electrode insulated from the semiconductor filler in the gate trench to contact with the gate insulating film, and

forming a source region of the first conductivity type on a surface within the opposite conductive region to contact with the gate insulating film.

2. The method of manufacturing a transistor according to claim 1, after growing a semiconductor material to a shallower position than a depth of the opposite conductive region in the deep trench, and forming the semiconductor filler with removing an upper portion of the semiconductor material.

3. The method of manufacturing a transistor according to claim 2, after forming the gate insulating film on the inner side surface and the bottom surface of the deep trench, growing the semiconductor material in the deep trench, before forming the gate insulating film, removing an upper portion of the insulating film, exposing the opposite conductive region on the inner side surface of the gate trench and forming the gate insulating film on the exposed the opposite conductive region.

4. The method of manufacturing a transistor according to claim 2, exposing the drain layer in the deep trench, growing the semiconductor material and forming a pn junction between the semiconductor filler and the dram layer.

5. The method of manufacturing a transistor according to claim 2, growing a silicon single crystal containing impurities of the second conductivity type as the semiconductor material.

6. The method of manufacturing a transistor according to claim 2, growing a polysilicon containing impurities of the second conductivity type as the semiconductor material.

7. The method of manufacturing a transistor according to claim 1, wherein the opposite conductive region is formed by diffusing impurities of the second conductivity type from a part of surface of the drain layer.

8. The method of manufacturing a transistor having

a drain layer of a first conductivity type,

an opposite conductive region of a second conductivity type in contact with the drain layer,

a gate trench formed on a deeper position than a depth of the opposite conductive region on a surface of the opposite conductive region,

a gate insulating film disposed on an inner side surface of the gate trench,

a gate electrode disposed on an inside of the gate trench and insulated from the opposite conductive region by the gate insulating film,

a source region of the first conductivity type on a surface within the opposite conductive region to contact with the gate insulating film and

comprising the steps of:

forming a deep trench having a deeper depth than a depth of the gate trench, and

disposing a semiconductor filler of the second conductivity type on inside of the deep trench, thereby making an upper part than a top of the semiconductor filler into the gate trench.

9. The method of manufacturing a transistor according to claim 8, after growing the semiconductor material of the second conductivity type in the deep trench, removing the upper portion of the semiconductor material and forming the semiconductor filler.

10. The method of manufacturing a transistor according to claim 9, after forming the gate insulating film on the inner side surface and the bottom surface of the deep trench, growing the semiconductor material in the deep trench, before forming the gate insulating film, removing the upper portion of the insulating film, exposing the opposite conductive region on the inner side surface of the gate trench and forming the gate insulating film on the exposed opposite conductive region.

11. The method of manufacturing a transistor according to claim 9, exposing the drain layer in the deep trench, growing the semiconductor material and forming a pn junction between the semiconductor filler and the drain layer.

12. The method of manufacturing a transistor according to claim 9, growing the silicon single crystal containing impurities of the second conductivity type as the semiconductor material.

13. The method of manufacturing a transistor according to claim 9, growing the polysilicon containing impurities of the second conductivity type as the semiconductor material.

14. The method of manufacturing a transistor according to claim 8, wherein the opposite conductive region is formed by diffusing impurities of the second conductivity type from a part of surface of the drain layer.