Programmable wake up of memory transfer controllers in a memory transfer engine

• US 6,708,259 B1
• Filed: 02/01/2002
• Issued: 03/16/2004
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: Cradle IP LLC
• Original Assignee: Cradle Technologies
• Inventors: Wyland, David C.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US10/061,543
• Time in Patent Office: 774 Days
• Field of Search: 711/147, 711/154
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

Methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. The first mechanism, Parameter List Pointer (PLP) FIFO Wake Up, wakes up an MTC after an external agent writes to an MTC'"'"'s PLP FIFO. This activates the MTC'"'"'s run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This mechanism allows the MTC to distinguish between multiple possible originators of multiple possible wake-up events; wake-up events may be queued. Events may be directed to particular MTCs or to the next MTC available to process the event. The second mechanism wakes up an MTC after an external agent writes to an MTC'"'"'s external wake-up address. This sets the MTC'"'"'s run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This approach only recognizes one event and one source. Events may not be queued using this approach.

Claims

1. In a semiconductor chip, a method of waking up an idle memory transfer controller in response to an event from an external source, said method comprising:

a) writing to at least one hardware register of a memory transfer engine including a plurality of memory transfer controllers, said writing performed by an external agent; and

b) activating an idle memory transfer controller so that it can execute instructions, said activation enabled by the writing step.

2. The method of claim 1 further including selecting a memory transfer controller to activate.

3. The method of claim 1 wherein the writing step identifies a specific memory transfer controller to be activated.

4. The method of claim 1 wherein the writing step does not specify which memory transfer controller is to be activated.

5. The method of claim 4 wherein the memory transfer controller to be activated is chosen in round-robin fashion.

6. The method of claim 1 wherein the activating step includes setting a run bit of the memory transfer controller.

7. The method of claim 4 further including a selection step, wherein one of the plurality of memory transfer controllers is chosen to execute an instruction.

8. The method of claim 1 wherein the hardware register is an external wake-up register.

9. The method of claim 1 wherein the hardware register is a command input buffer for the memory transfer engine.

10. The method of claim 1 wherein the activating step is performed by memory transfer controller start logic.

11. The method of claim 1 wherein at least one of the plurality of memory transfer controllers is idle when the writing step occurs.

12. The method of claim 1 wherein none of the plurality of memory transfer controllers is idle when the writing step occurs.

13. The method of claim 12 wherein the activating step occurs after a memory transfer controller becomes idle.

14. In a semiconductor chip, a method of causing an idle memory transfer controller to execute instructions in response to an event from an external source, said method comprising:

a) writing to at least one hardware register of a memory transfer engine including a plurality of memory transfer controllers, said writing performed by an external agent;

b) setting a first bit in an idle memory transfer controller, thereby activating said memory transfer controller; and

c) executing instructions.

15. The method of claim 14 wherein the hardware register is a command input buffer of the memory transfer engine.

16. The method of claim 14 wherein the hardware register is an external wake-up register.

17. The method of claim 14 wherein the external agent writes to two hardware registers of the memory transfer engine.

18. The method of claim 15 wherein a value written to the command input buffer defines an event type.

19. The method of claim 15 wherein a value written to a second hardware register defines an event originator.

20. The method of claim 15 wherein a plurality of values may be queued in the command input buffer, said values defining a plurality of events.

21. The method of claim 14 wherein at least one of the plurality of memory transfer controllers is idle when the writing step occurs.

22. The method of claim 14 wherein none of the plurality of memory transfer controllers is idle when the writing step occurs.

23. The method of claim 22 wherein the activating step occurs after a memory transfer controller becomes idle.

24. In a semiconductor chip, a method of operating a memory transfer engine including a plurality of memory transfer controllers and a shared processor in an event-driven fashion, said method comprising:

a) executing initialization code with the processor;

b) stopping the executing memory transfer controller such that the processor is surrendered by said executing memory transfer controller;

c) writing to a hardware register of a memory transfer engine, said writing performed by an external agent, wherein the value written to the hardware register identifies an event type; and

d) activating an idle memory transfer controller so that it can execute instructions with the processor, said activation enabled by the writing step.

25. The method of claim 24 further including a selection step, wherein one of the plurality of memory transfer controllers is chosen to be activated.

26. The method of claim 24 wherein the writing step identifies a specific memory transfer controller to be activated.

27. The method of claim 24 wherein the writing step does not identify a specific memory transfer controller to be activated.

28. The method of claim 24 wherein at least one of the plurality of memory transfer controllers is idle when the writing step occurs.

29. The method of claim 24 wherein none of the plurality of memory transfer controllers is idle when the writing step occurs.

30. The method of claim 29 wherein the activating step occurs after a memory transfer controller becomes idle.