Field effect transistor and method of its manufacture

• US 6,710,406 B2
• Filed: 05/24/2002
• Issued: 03/23/2004
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mo, Brian Sze-Ki, Chau, Duc, Sapp, Steven, Bencuya, Izak, Probst, Dean Edward
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US10/155,554
• Publication Number:
  US 20020140027A1
• Time in Patent Office: 669 Days
• Field of Search: 257/331, 257/341
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A trenched field effect transistor comprising:

a semiconductor substrate having dopants of a first conductivity type;

a trench extending to a first depth into said semiconductor substrate;

a pair of doped source junctions having dopants of the first conductivity type, and positioned on opposite sides of the trench;

a doped well having dopants of a second conductivity type opposite to said first conductivity type, and formed into the substrate to a second depth that is less than said first depth of the trench; and

a heavy body formed in said doped well extending to a third depth that is less than said second depth of said doped well, the heavy body forming an abrupt junction with the well;

wherein, a location of the abrupt junction relative to the depth of the well is adjusted so that a transistor breakdown initiation point is spaced away from the trench in the semiconductor, when voltage is applied to the transistor.

2. The trenched field effect transistor of claim 1 wherein said doped well has a substantially flat bottom.

3. The trenched field effect transistor of claim 1 wherein said trench has rounded top and bottom corners.

4. The trenched field effect transistor of claim 1 wherein the abrupt junction causes the transistor breakdown initiation point to occur in the area of the junction, when voltage is applied to the transistor.

5. The trenched field effect transistor of claim 1 wherein the heavy body comprises a heavily doped region having dopants of the second conductivity type at the abrupt junction.

6. The trenched field effect transistor of claim 5 wherein the heavily doped region is formed by implanting dopants of the second conductivity type at approximately the third depth.

7. The trenched field effect transistor of claim 1 further comprising a deep doped region having dopants of the second conductivity type, the deep doped region extending into the substrate to a fourth depth that is deeper than said first depth of the trench.

8. The trenched field effect transistor of claim 7 wherein said deep doped region forms a PN junction diode with the substrate.

9. The trenched field effect transistor of claim 7 wherein the deep doped region forms a termination structure.

10. The trenched field effect transistor of claim 1 wherein the trench is lined with a dielectric layer and substantially filled with conductive material.

11. The trenched field effect transistor of claim 10 wherein the conductive material comprises polysilicon.

12. The trenched field effect transistor of claim 10 wherein the conductive material filling the trench is recessed relative to the surface of the semiconductor substrate.

13. A field effect transistor comprising:

a semiconductor substrate having dopants of a first conductivity type;

a plurality of gate-forming trenches arranged substantially parallel to each other, each trench extending to a first depth into said substrate, the space between adjacent trenches defining a contact area;

a pair of doped source junctions positioned on opposite sides of each trench, the source junctions having dopants of the first conductivity type;

a doped well having dopants of a second conductivity type with a charge opposite that of the first conductivity type, the doped well being formed in the semiconductor substrate between each pair of gate-forming trenches;

a heavy body formed inside the doped well and having a second depth that is less than the first depth of the trenches; and

heavy body contact regions defined at the surface of the semiconductor substrate along the length of the contact area,

wherein the heavy body forms an abrupt junction with the well, and the depth of the heavy body relative to a depth of the well is adjusted so that breakdown of the transistor originates in the semiconductor in a region spaced away from the trenches when voltage is applied to the transistor.

14. The field effect transistor of claim 13, wherein each said doped well has a substantially flat bottom.

15. The field effect transistor of claim 13 wherein the adjusted depth of the junction causes the breakdown origination point to occur approximately halfway between adjacent gate-forming trenches.

16. The field effect transistor of claim 13 wherein each said doped well has a depth less than the first depth of said gate-forming trenches.

17. The field effect transistor of claim 13 wherein each said gate-forming trench has rounded top and bottom corners.

18. The field effect transistor of claim 13 further comprising a deep doped region having dopants of the second conductivity type, the deep doped region extending into the substrate to a depth greater than said first depth of the said plurality of gate-forming trenches.

19. The field effect transistor of claim 18 wherein the deep doped region forms a PN junction diode with the substrate.

20. The field effect transistor of claim 19 wherein the deep doped region forms a field termination structure surrounding the periphery of the plurality of gate-forming trenches.

21. The field effect transistor of claim 20 further comprising:

a layer of dielectric material formed over the deep doped region; and

a layer of conductive material formed on top of the layer of dielectric material.

22. The field effect transistor of claim 13 further comprising a field termination structure including a termination trench extending continuously around the periphery of the plurality of gate-forming trenches.

23. The field effect transistor of claim 22 wherein said field termination structure comprises a plurality of concentrically arranged termination trenches.

24. The field effect transistor of claim 13 wherein the heavy body forms a continuous doped region along substantially the entire length of said contact area.

25. The field effect transistor of claim 13 wherein said doped source regions extend along the length of the trench.

26. The field effect transistor of claim 25 further comprising a source contact region defined at the surface of the semiconductor substrate and configured to contacting the doped source regions.

27. The field effect transistor of claim 25 further comprising a plurality of source contact regions disposed along the length of the contact area in an alternating fashion with the plurality of heavy body contact regions.

28. The field effect transistor of claim 13 wherein between a pair of adjacent trenches, the heavy body is bounded by the pair of adjacent trenches and the doped source regions.

29. The field effect transistor of claim 13 wherein between a pair of adjacent trenches, the heavy body extends continuously parallel to the longitudinal axis of the trenches.

30. The field effect transistor of claim 13 further comprising:

a layer of dielectric lining inside walls of each of said plurality of gate-forming trenches; and

a layer of conductive material substantially filling the gate-forming trenches.

31. The field effect transistor of claim 30 wherein the layer of conductive material comprises polysilicon.

32. The field effect transistor of claim 30 wherein the top surface of the layer of conductive material substantially filling the gate-forming trenches is recessed relative to the top surface of the semiconductor substrate.