Methods for polymer removal following etch-stop layer etch
First Claim
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1. A method for creating an interconnect structure associated with a semiconductor wafer, the method comprising:
- forming a cavity in a dielectric layer over the semiconductor wafer to expose a portion of an etch-stop layer underlying the dielectric layer;
performing an etch-stop etch process to remove the exposed portion of the etch-stop layer in the cavity and to expose a portion of a conductive feature underlying the etch-stop layer; and
removing polymer from sidewalls in the cavity after the etch-stop etch process using a plasma comprising hydrogen or a hydrogen-containing gas and one of argon, helium, neon, and xenon.
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Abstract
Cleaning methods are disclosed for removing sidewall polymers from interconnect vias or trenches, wherein a wafer is exposed to a plasma comprising hydrogen and an inert gas in a plasma cleaning chamber following etch-stop etching.
42 Citations
28 Claims
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1. A method for creating an interconnect structure associated with a semiconductor wafer, the method comprising:
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forming a cavity in a dielectric layer over the semiconductor wafer to expose a portion of an etch-stop layer underlying the dielectric layer;
performing an etch-stop etch process to remove the exposed portion of the etch-stop layer in the cavity and to expose a portion of a conductive feature underlying the etch-stop layer; and
removing polymer from sidewalls in the cavity after the etch-stop etch process using a plasma comprising hydrogen or a hydrogen-containing gas and one of argon, helium, neon, and xenon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
wherein the wafer comprises a conductive feature formed over a substrate, a lower etch-stop layer formed of silicon carbide material over the conductive feature, a lower dielectric layer farmed of organo-silicate glass material over the lower etch-stop layer, an upper etch-stop layer formed over the lower dielectric layer, an upper dielectric layer formed over the upper etch-stop layer, and a hard mask layer formed over the upper dielectric layer;
wherein forming the cavity comprises etching a via through first portions of the hard mask layer, the upper dielectric layer, the upper etch-stop layer, and the lower dielectric layer to expose a first portion of the tower etch-stop layer in a prospective via region of the wafer, and etching a trench through second portions of the hard mask layer and the upper dielectric layer to expose a second portion of the upper etch-stop layer in a prospective trench region of the wafer; and
wherein performing the etch-stop etch process comprises removing the exposed first portion of the lower etch-stop layer to expose the portion of the conductive feature in the prospective via region.
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18. The method of claim 17, further comprising forming a barrier layer in the cavity, filling the cavity with conductive material, and planarizing the wafer following removal of the polymer from the sidewalls.
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19. The method of claim 14, wherein removing polymer from sidewalls comprises creating the plasma and exposing the wafer to the plasma in the plasma cleaning chamber for about 20 seconds or more and about 40 seconds or less using a gas flow rate of about 3000 sccm or more and about 4000 sccm or less, a chamber temperature of about 250 degrees C., and a pressure of about 0.5 torr or more and about 1.0 torr or less.
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20. A method of removing polymer from a cavity during formation of Interconnect structures in the manufacture of a semiconductor wafer, the method comprising:
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etching an exposed portion of an etch-stop layer in the cavity in a first process chamber to expose a portion of a conductive feature underlying the etch-stop layer; and
removing polymer from sidewalls in the cavity in a second process chamber using a plasma comprising hydrogen and one of the following gases;
argon, helium, neon, or xenon.- View Dependent Claims (21, 22)
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23. A method of cleaning polymer from a cavity in a dual damascene interconnect structure of a semiconductor wafer, comprising;
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placing the wafer in a plasma cleaning chamber; and
exposing the wafer to a plasma comprising hydrogen or other hydrogen-containing gas and one of argon, helium, neon, and xenon in the plasma cleaning chamber. - View Dependent Claims (24)
creating the plasma in the plasma cleaning chamber using a nitrogen-free gas comprising about 60% hydrogen and about 40% argon; and
exposing the wafer to the plasma in the plasma cleaning chamber for about 20 seconds or more and about 40 seconds or less using a gas flow rate of about 3000 sccm or more and about 4000 sccm or less, a chamber temperature of about 250 degrees C., and a pressure of about 0.5 torr or more and about 1.0 torr or less.
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25. A method of cleaning polymer from a cavity in a single damascene interconnect structure of a semiconductor wafer, comprising:
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placing the wafer in a plasma cleaning chamber; and
exposing the wafer to a plasma comprising hydrogen or other hydrogen-containing gas and one of argon, helium, neon, and xenon in the plasma cleaning chamber. - View Dependent Claims (26)
creating the plasma in the plasma cleaning chamber using a nitrogen-free gas comprising about 60% hydrogen and about 40% argon; and
exposing the wafer to the plasma in the plasma cleaning chamber for about 20 seconds or more and about 40 seconds or less using a gas flow rate of about 3000 sccm or more and about 4000 sccm or less, a chamber temperature of about 250 degrees C., and a pressure of about 0.5 torr or more and about 1.0 torr or less.
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27. A method of cleaning polymer from a cavity in a semiconductor wafer, comprising:
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performing an etch process which leaves polymeric residue in a cavity in the wafer; and
exposing the wafer to a plasma comprising hydrogen or other hydrogen-containing gas and one of argon, helium, neon, and xenon to remove at least a portion of the polymeric residue from the cavity. - View Dependent Claims (28)
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Specification