SOI CMOS device with reduced DIBL

• US 6,716,682 B1
• Filed: 10/10/2002
• Issued: 04/06/2004
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra V.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/268,578
• Time in Patent Office: 544 Days
• Field of Search: 438/149, 438/154, 438/217, 438/459, 257/347
• US Class Current: 438/149
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Claims

1. A method of creating complementary transistor devices each having a retrograde doping profile in an active layer of silicon positioned above a buried oxide (BOX) layer, the method comprising:

implanting dopants through device regions of the active layer into the BOX layer so as to form dopant source regions comprising borophosphosilicate glass (BPSG) within the BOX layer substantially adjacent the interface between the BOX layer and the active layer;

implanting dopants into gate regions of the device regions so as to adjust threshold voltages of the complementary devices;

forming complementary transistor devices in the active layer so that the transistor devices have a channel region in the active layer and a gate positioned over the channel region; and

forming a passivation layer over the transistor devices with a high temperature process wherein the forming of the passivation layer results in high temperature processing of the dopant source regions such that dopant diffuses out of the dopant source regions into the channel regions to thereby define retrograde doping profiles in the channel regions.

2. The method of claim 1, wherein the active layer comprises a layer of epitaxial silicon.

3. The method of claim 1, wherein the buried oxide layer comprises a layer of silicon that is implanted with oxygen and thermally processed so as to oxidize a buried layer of silicon.

4. The method of claim 1, wherein the transistor devices comprises a source positioned adjacent the gate and the channel region and a drain positioned adjacent the gate and the channel region and opposite the source.

5. The method of claim 4, wherein the source and drain comprise regions of the active layer which are doped complementarily to the channel region.