Three-dimensional memory

• US 6,717,222 B2
• Filed: 08/28/2002
• Issued: 04/06/2004
• Est. Priority Date: 10/07/2001
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Ngô , Ngân V.
• Application Number:
  US10/230,648
• Publication Number:
  US 20030067043A1
• Time in Patent Office: 587 Days
• Field of Search: 257/390, 257/401, 257/67, 257/211
• US Class Current: 257/390
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/822 for read only memories
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

One greatest advantage of the three-dimensional memory (3D-M) is its integratibility. In a three-dimensional integrated memory (3DiM), the 3D-M is integrated with an embedded RWM and/or an embedded processor. Collectively, the 3DiM excels in speed, density/cost, programmability and data security. The present invention makes further improvements to three-dimensional mask-programmable read-only memory. Another 3D-M application of great importance is in the area of IC-testing. The 3D-M carrying test vectors can be integrated with the circuit-under-test, thus supporting field self-test and at-speed test.

Claims

1. A non-electrically programmable three-dimensional integrated memory (NEP-3DiM), comprising:

a substrate circuit, said substrate circuit further comprising a substrate integrated circuit and an address-decoder, said substrate integrated circuit comprising an embedded RWM and/or an embedded processor;

at least a non-electrically programmable three-dimensional memory (NEP-3DM) level, said NEP-3DM level being stacked on top of said substrate circuit and connected with said substrate circuit through a plurality of inter-level connecting vias, said address-decoder decoding address for at least a portion of said NEP-3DM level.

2. The NEP-3DiM according to claim 1, wherein

said embedded RWM comprises an embedded RAM, at least a portion of the input/output of said embedded RAM being eventually connected with at least a portion of the input/output of said address-decoder, whereby said embedded RAM stores a copy of the data from said NEP-3DM.

3. The NEP-3DiM according to claim 1, wherein

said embedded RWM comprises an embedded ROM, whereby said embedded ROM stores correctional data for said NEP-3DM level;

and

said substrate circuit further comprises means for selecting data from said NEP-3DM level or from said embedded ROM.

4. The NEP-3DiM according to claim 1, wherein

said embedded RWM comprises an embedded ROM, whereby said embedded ROM stores upgrade codes for said NEP-3DM level;

and

said substrate circuit further comprises means for selecting data from said NEP-3DM level or from said embedded ROM.

5. The NEP-3DiM according to claim 1, wherein

at least a portion of said embedded RWM and at least a portion of said NEP-3DM form a unified memory space;

and

said substrate circuit further comprises an address-translation block and an address-decoder for said unified memory space, at least a portion of the output of said address-translation block being eventually connected with at least a portion of the input of said address-decoder for said unified memory space.

6. The NEP-3DiM according to claim 1, wherein

said embedded processor is selected from a group consisting of D/A converter, decoder and decryption engine.

7. A non-electrically programmable three-dimensional memory (NEP-3DM), comprising:

a substrate circuit, said substrate circuit comprising a plurality of active devices and an interconnect system connecting said active devices, said substrate circuit further comprising an address-decoder;

at least an NEP-3DM level stacked on top of said substrate circuit and connected with said substrate circuit through a plurality of inter-level connecting vias, said NEP-3DM level comprising a plurality of address-selection lines and NEP-3DM cells, said address-decoder decoding address for at least a portion of said NEP-3DM level.

8. The NEP-3DM according to claim 7, wherein

said address-selection lines in said NEP-3DM level comprises poly-crystalline semiconductor materials; and

said interconnect system of said substrate circuit is made of refractory conductor and thermally-stable dielectric.

9. The NEP-3DM according to claim 7, further comprising a shielding layer between said substrate circuit and at least a portion of said NEP-3DM level.

10. The NEP-3DM according to claim 7, further comprising:

at least an interconnect gap between two adjacent address-selection lines on said NEP-3DM level;

at least an embedded wire, said embedded wire passing through said NEP-3DM level in said interconnect gap.

11. The NEP-3DM according to claim 7, further comprising at least a routing level in said interconnect system of said substrate circuit, said routing level providing electrical connection between said NEP-3DM level and said substrate circuit, whereby at least a portion of said address-decoder is located under said NEP-3DM level.

12. The NEP-3DM according to claim 7, wherein

at least an address-selection line in said NEP-3DM level is a composite line, said composite line comprising a highly-conductive layer and a lightly-doped layer, said lightly-doped layer being located at the bottom of said composite line;

and

said NEP-3DM further comprises a via and an inverted-U linK said via being located near one end of said composite line and said inverted-U link having an inverted-U shape, said via being connected with said composite line through said inverted-U link by making contacts to said highly-conductive layer on top and/or on sidewalls.