Method and apparatus for minimizing latency in digital signal processing systems

  • US 6,717,537 B1
  • Filed: 06/24/2002
  • Issued: 04/06/2004
  • Est. Priority Date: 06/26/2001
  • Status: Active Grant
First Claim
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1. A digital closed feedback loop having an input, an output, a first summation node, and a second summation node, wherein a processed digital input signal is fed to a first input of the first summation node, the processed digital input signal has an intermediate sampling rate, and a disturbance signal is fed to a first input of the second summation node, the digital closed feedback loop comprising:

  • a compensation filter having an input coupled to an output of the first summation node;

    a digital-to-analog converter having an input coupled to an output of the compensation filter;

    an output transducer having an input coupled to an output of the digital-to-analog converter and having an output coupled to a second input of the second summation node;

    an input transducer having an input coupled to an output of the second summation node;

    a delta-sigma modulator having an input coupled to an output of the input transducer, wherein the output signal of the delta-sigma modulator has a first sampling rate that is higher than the intermediate sampling rate; and

    a feedback sampling-rate converter having an input coupled to an output of the delt-asigma modulator and having an output coupled to a second input of the first summation node, wherein the output signal of the delta-sigma modulator is down-sampled from the first sampling rate to the intermediate sampling rate.

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