Method and apparatus for minimizing latency in digital signal processing systems

• US 6,717,537 B1
• Filed: 06/24/2002
• Issued: 04/06/2004
• Est. Priority Date: 06/26/2001
• Status: Expired due to Term

• Current Assignee: Bose Corporation
• Original Assignee: Sonic Innovations Incorporated (William Demant Fonden)
• Inventors: Johnson, Martin R., Fang, Xiaoling, Davis, Keith L.
• Primary Examiner(s): JeanGlaude, Jean Bruner
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US10/179,930
• Time in Patent Office: 652 Days
• Field of Search: 341/143, 341/155, 341/144, 381/94, 381/55, 381/92
• US Class Current: 341/143
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

A method and an apparatus for minimizing latency in digital signal processing paths. One example is an active noise cancellation device. The system includes a digital closed feedback loop having a forward path and a feedback path. The forward path includes a compensation filter, a digital-to-analog converter, and an output transducer. The feedback path includes an input transducer, a feedback delta-sigma modulator, and a feedback sampling-rate converter. An input signal is processed in one of several ways into a processed digital input signal having a preselected intermediate sampling rate. Through the feedback path, an analog output signal is processed into a digital feedback signal having substantially the same preselected intermediate sampling rate. The processed digital input signal and the digital feedback signal are combined and processed through the forward path to produce an anti disturbance signal that is combined with a disturbance signal to form the analog output signal.

Claims

1. A digital closed feedback loop having an input, an output, a first summation node, and a second summation node, wherein a processed digital input signal is fed to a first input of the first summation node, the processed digital input signal has an intermediate sampling rate, and a disturbance signal is fed to a first input of the second summation node, the digital closed feedback loop comprising:

a compensation filter having an input coupled to an output of the first summation node;

a digital-to-analog converter having an input coupled to an output of the compensation filter;

an output transducer having an input coupled to an output of the digital-to-analog converter and having an output coupled to a second input of the second summation node;

an input transducer having an input coupled to an output of the second summation node;

a delta-sigma modulator having an input coupled to an output of the input transducer, wherein the output signal of the delta-sigma modulator has a first sampling rate that is higher than the intermediate sampling rate; and

a feedback sampling-rate converter having an input coupled to an output of the delt-asigma modulator and having an output coupled to a second input of the first summation node, wherein the output signal of the delta-sigma modulator is down-sampled from the first sampling rate to the intermediate sampling rate.

2. The digital closed feedback loop according to claim 1, further comprising an input processor for transforming an input signal into the processed digital input signal.

3. The digital closed feedback loop according to claim 2, wherein the input processor further comprises:

an input delta-sigma modulator having an input that receives the input signal, wherein the input signal is modulated to a second sampling rate that is higher than the intermediate sampling rate;

a first input sampling-rate converter having an input coupled to an output of the input delta-sigma modulator, wherein the second sampling rate is down-sampled to a third sampling rate; and

an equalizer having an input coupled to an output of the first input sampling-rate converter.

4. The digital closed feedback loop according to claim 3, wherein the third sampling rate is equal to the intermediate sampling rate and the output signal from an output of the equalizer is the processed digital input signal.

5. The digital closed feedback loop according to claim 3, wherein the third sampling rate is less than the intermediate sampling rate and the input processor further comprises:

a second input sampling-rate converter having an input coupled to an output of the equalizer, wherein the third sampling rate is up-sampled to the intermediate sampling rate and the output signal from an output of the second input sampling-rate converter is the processed digital input signal.

6. The digital closed feedback loop according to claim 2, wherein the input processor further comprises:

an input delta-sigma modulator having an input that receives the input signal, wherein the input signal is modulated to a second sampling rate that is higher than the intermediate sampling rate; and

an input sampling-rate converter having an input coupled to an output of the input delta-sigma modulator, wherein the second sampling rate is down-sampled to the intermediate sampling rate and the output signal from an output of the input sampling-rate converter is the processed digital input signal.

7. The digital closed feedback loop according to claim 2, wherein the input processor further comprises:

an equalizer having an input that receives the input signal and having an output that is the source of the processed digital input signal.

8. The digital closed feedback loop according to claim 2, wherein the input processor further comprises:

an equalizer having an input that receives the input signal; and

an input sampling-rate converter having an input coupled to an output of the equalizer, wherein the input signal is converted from a second sampling rate to the intermediate sampling rate and the output signal from an output of the input sampling-rate converter is the processed digital input signal.

9. The digital closed feedback loop according to claim 2, wherein the input processor further comprises:

an input sampling-rate converter having an input that receives the input signal and having an output that is the source of the processed digital input signal, wherein the input signal is converted from a second sampling rate to the intermediate sampling rate.

10. A digital closed feedback loop having an input, an output, a first summation node, and a second summation node, wherein a processed digital input signal is fed to a first input of the first summation node, the processed digital input signal has an intermediate sampling rate, and a disturbance signal is fed to a first input of the second summation node, the digital closed feedback loop comprising:

a digital-to-analog converter having an input coupled to an output of the first summation node;

an output transducer having an input coupled to an output of the digital-to-analog converter and having an output coupled to a second input of the second summation node;

an input transducer having an input coupled to an output of the second summation node;

a delta-sigma modulator having an input coupled to an output of the input transducer, wherein the output signal of the delta-sigma modulator has a first sampling rate that is higher than the intermediate sampling rate;

a feedback sampling-rate converter having an input coupled to an output of the delta-sigma modulator, wherein the output signal of the delta-sigma modulator is down-sampled from the first sampling rate to the intermediate sampling rate; and

a compensation filter having an input coupled to an output of the feedback sampling-rate converter and having an output coupled to a second input of the first summation node.

11. The digital closed feedback loop according to claim 10, further comprising an input processor for transforming an input signal into the processed digital input signal.

12. The digital closed feedback loop according to claim 11, wherein the input processor further comprises:

an input delta-sigma modulator having an input that receives the input signal, wherein the input signal is modulated to a second sampling rate that is higher than the intermediate sampling rate;

a first input sampling-rate converter having an input coupled to an output of the input delta-sigma modulator, wherein the second sampling rate is down-sampled to a third sampling rate; and

an equalizer having an input coupled to an output of the first input sampling-rate converter.

13. The digital closed feedback loop according to claim 12, wherein the third sampling rate is equal to the intermediate sampling rate and the output signal from an output of the equalizer is the processed digital input signal.

14. The digital closed feedback loop according to claim 12, wherein the third sampling rate is less than the intermediate sampling rate and the input processor further comprises:

a second input sampling-rate converter having an input coupled to an output of the equalizer, wherein the third sampling rate is up-sampled to the intermediate sampling rate and the output signal from an output of the second input sampling-rate converter is the processed digital input signal.

15. The digital closed feedback loop according to claim 11, wherein the input processor further comprises:

an input delta-sigma modulator having an input that receives the input signal, wherein the input signal is modulated to a second sampling rate that is higher than the intermediate sampling rate; and

an input sampling-rate converter having an input coupled to an output of the input delt-asigma modulator, wherein the second sampling rate is down-sampled to the intermediate sampling rate and the output signal from an output of the input sampling-rate converter is the processed digital input signal.

16. The digital closed feedback loop according to claim 11, wherein the input processor further comprises:

an equalizer having an input that receives the input signal and having an output that is the source of the processed digital input signal.

17. The digital closed feedback loop according to claim 11, wherein the input processor further comprises:

an equalizer having an input that receives the input signal; and

an input sampling-rate converter having an input coupled to an output of the equalizer, wherein the input signal is converted from a second sampling rate to the intermediate sampling rate and the output signal from an output of the input sampling-rate converter is the processed digital input signal.

18. The digital closed feedback loop according to claim 11, wherein the input processor further conprises:

an input sampling-rate converter having an input that receives the input signal and having an output that is the source of the processed digital input signal, wherein the input signal is converted from a second sampling rate to the intermediate sampling rate.

19. A digital closed feedback loop method comprising:

processing an input signal into a processed digital input signal having a preselected intermediate sampling rate;

converting an analog output signal into a digital feedback signal having substantially the same preselected intermediate sampling rate;

combining the processed digital input signal and the digital feedback signal to form a combined digital signal;

generating a digital anti disturbance signal from the combined digital signal;

converting the digital anti disturbance signal to an analog anti disturbance signal; and

combining the analog anti disturbance signal with a disturbance signal to form the analog output signal.