Method of fabrication and device for electromagnetic-shielding structures in a damascene-based interconnect scheme

• US 6,720,245 B2
• Filed: 09/06/2001
• Issued: 04/13/2004
• Est. Priority Date: 09/07/2000
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Stucchi, Michele, De Roest, David, Maex, Karen
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US09/948,370
• Publication Number:
  US 20020102835A1
• Time in Patent Office: 950 Days
• Field of Search: 438/618, 438/622, 438/631, 438/637, 438/422, 438/614, 438/633, 438/666, 438/430, 438/619, 257/758, 257/773
• US Class Current: 438/614
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A shielded interconnect and a method of manufacturing a shielded interconnect implemented in a damascene back-end-of-line technology to form electromagnetically shielded interconnects. The standard metallization of the damascene technology is used as a core layer in a coaxial interconnect line. Prior to filling the via and trench openings in the damascene stack with this standard metallization, conductive and dielectric layers are formed as shield and insulator layers, respectively, of the coaxial interconnect line.

Claims

1. A method of forming a shielded interconnect on a substrate covered with a stack, the method comprising the steps of:

forming an opening in the stack on the substrate, the substrate comprising at least one active device and the stack comprising at least one insulation layer covering the substrate, wherein the opening is formed at a level above the at least one active device;

depositing a first conductive layer over the stack;

depositing a first dielectric layer over the first conductive layer;

depositing a second conductive layer over the first dielectric layer, and

polishing the substrate until at least a portion of the stack is exposed.

2. The method of claim 1, further comprising depositing a barrier layer between the first dielectric layer and the second conductive layer.

3. The method of claim 1, wherein the step of forming an opening includes patterning a trench for a core damascene metal stack.

4. The method of claim 1, wherein the step of forming an opening includes forming a trench having a bottom portion and two sidewalls, wherein the thickness of the first conductive layer in the bottom portion and two sidewalls is substantially the same.

5. The method of claim 1, wherein the step of depositing a first conductive layer includes depositing at least one of a metal and metal alloy, formed by sputtering, plasma vapor deposition (PVD), and/or chemical vapor deposition (CVD).

6. The method of claim 1, wherein the step of depositing a first conductive layer includes depositing a conductive shield layer having a thickness in the range of 50 to 500 nanometers.

7. The method of claim 1, wherein the step of depositing the first dielectric layer includes depositing a layer comprising at least one of silicon, oxide, nitride, and carbide layers.

8. The method of claim 1, wherein the step of depositing the first dielectric layer includes depositing an insulation layer having a thickness in the range of 10 to 500 nanometers.

9. The method of claim 1, wherein the step of depositing the second conductive layer includes depositing a core layer comprising copper.

10. The method of claim 1, wherein said stack further comprises a first hard mask layer located under the first conductive layer, a second dielectric layer located under the first hard mask layer, a second hard mask layer located under the second dielectric layer, and a third dielectric layer located under the second hard mask layer.

11. The method of claim 10, wherein the step of polishing the substrate comprises exposing at least one of the second dielectric layer or the first hard mask layer of the substrate.

12. The method of claim 1, further comprising confining the first dielectric layer and second conductor layer to within the opening in the stack of the substrate.

13. A shielded interconnect formed on a substrate covered with a stack comprising the shielded interconnect being manufactured by a method comprising the steps of:

forming an opening in the stack on the substrate, the substrate comprising at least one active device and the stack comprising at least one insulation layer covering the substrate, wherein the opening is formed at a level above the at least one active device;

depositing a first conductive layer over the stack;

depositing a dielectric layer over the first conductive layer;

depositing a second conductive layer over the dielectric layer, and polishing the substrate until at least a portion of the stack is exposed.

14. A shielded interconnect, comprising:

a first conductive layer deposited in an opening of a stack comprising at least one insulating layer and formed on a substrate comprising at least one active device, wherein the opening is at a level above the at least one active device;

a dielectric layer deposited over the first conductive layer; and

a second conductive layer deposited over the dielectric layer, wherein at least a portion of the stack is exposed.

15. The shielded interconnect of claim 14, further comprising a barrier layer deposited between the dielectric layer and the second conductive layer.

16. The shielded interconnect of claim 14, wherein the opening comprises a trench patterned in the stack for a core damascene metal stack.

17. The shielded interconnect of claim 14, wherein the opening is defined by a bottom portion and two sidewalls, and wherein the thickness of the first conductive layer in the bottom portion and two sidewalls is substantially the same.

18. The shielded interconnect of claim 14, wherein the first conductive layer comprises at least one of a metal and metal alloy, formed by sputtering, plasma vapor deposition (PVD), and/or chemical vapor deposition (CVD).

19. The shielded interconnect of claim 14, wherein the exposed portion includes at least one of a dielectric layer or a hard mask layer of the substrate.

20. The shielded interconnect of claim 14, wherein the dielectric layer and second conductor layer are confined to within the opening in the stack of the substrate.