Duplexer structure for coupling a transmitter and a receiver to a common antenna

• US 6,721,544 B1
• Filed: 11/09/2000
• Issued: 04/13/2004
• Est. Priority Date: 11/09/2000
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel Corporation
• Inventors: Franca-Neto, Luiz M.
• Primary Examiner(s): Chin, Vivian
• Assistant Examiner(s): CRAVER, CHARLES R
• Application Number:
  US09/711,344
• Time in Patent Office: 1,251 Days
• Field of Search: 455/83, 455/78, 455/425, 455/121, 455/129, 455/269, 455/271, 455/283, 455/280, 455/284, 455/344, 455/340, 333/172, 343/749, 343/750, 343/822, 343/852, 343/850, 343/860, 343/861
• US Class Current: 455/83
• CPC Class Codes: H04B 1/52 Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa

Abstract

A duplexer structure for allowing an RF transmitter and an RF receiver to share a common antenna includes impedance matching circuitry to match the receiver input impedance to the antenna impedance during a receive operation and impedance transformation circuitry to transform the antenna impedance to a lower impedance at the receiver input terminals during a transmit operation. The impedance matching circuitry and the impedance transformation circuitry of the duplexer share one or more passive components, thus reducing the overall number of components required to implement the duplexer. This reduction in component count reduces the amount of chip area required to implement the duplexer and increases the ease with which the RF transceiver is integrated onto a semiconductor chip. In one embodiment, the duplexer uses a differential topology to provide common mode noise rejection and even harmonic distortion cancellation within a transceiver.

Claims

1. A duplexer to allow a receiver and a transmitter to share a common antenna comprising:

an antenna port to connect the duplexer to an antenna;

a receiver port to connect the duplexer to a receiver;

a transmitter port to connect the duplexer to a transmitter;

an interconnect to couple said transmitter port to said receiver port; and

a reconfigurable network coupled to said antenna port, said receiver port and said transmitter port, said reconfigurable network to provide an impedance matching circuit between the antenna and the receiver during a receive operation and to provide an impedance transformation circuit between the antenna and the transmitter during a transmit operation, said impedance transformation circuit comprising an inductor coupled to a capacitor and said impedance matching circuit comprising the inductor counted to the capacitor that is removed from the reconfigurable network.

2. The duplexer claimed in claim 1, wherein;

said impedance transformation circuit is to transform an antenna impedance at said antenna port to a significantly lower impedance at said transmitter port.

3. The duplexer claimed in claim 1, wherein:

said impedance matching circuit is to match a receiver input impedance at said receiver port to an antenna impedance at said antenna port.

4. The duplexer claimed in claim 1, wherein:

said reconfigurable network includes a switch to switch between said impedance matching circuit and said impedance transformation circuit in response to a control signal.

5. The duplexer claimed in claim 1, wherein:

said interconnect includes at least one switch to connect said transmitter port to said receiver port in response to a control signal.

6. The duplexer claimed in claim 1, wherein:

said interconnect includes at least one pass gate to connect said transmitter port to said receiver port in response to a control signal, said at least one pass gate including an NMOS transistor and a PMOS transistor.

7. The duplexer claimed in claim 1, wherein:

said interconnect includes at least one conductive line to directly connect said transmitter port to said receiver port.

8. The duplexer claimed in claim 1, wherein:

said antenna port, said receiver port, and said transmitter port each include first and second differential terminals.

9. A duplexer to allow a receiver and a transmitter to share a common antenna comprising:

first and second antenna terminals to connect the duplexer to an antenna;

first and second receiver terminals to connect the duplexer to a receiver, first and second transmitter terminals to connect the duplexer to a transmitter;

a first interconnect to couple said first transmitter terminal to said first receiver terminal;

a second interconnect to couple said second transmitter terminal to said second receiver terminal; and

a switchable network connected between said first and second receiver terminals and said first and second antenna terminals, said switchable network including at least one switch for changing said switchable network between first and second configurations, said first configuration of said switchable network to match an antenna impedance at said first and second antenna terminals to a receiver input impedance at said first and second receiver terminals and said second configuration of said switchable network to transform said antenna impedance at said first and second antenna terminals to a significantly lower impedance at said first and second transmitter terminals, said second configuration of said switchable network including a differential L match circuit between said first and second antenna terminals and said first and second receiver terminals.

10. The duplexer claimed in claim 9, wherein:

said first and second configurations of said switchable network share at least one passive circuit element.

11. The duplexer claimed in claim 9, wherein:

said first interconnect includes a conductive line to directly connect said first transmitter terminal to said first receiver terminal.

12. The duplexer claimed in claim 9, wherein,

said first interconnect includes a transistor to controllably couple said first transmitter terminal to said first receiver terminal.

13. The duplexer claimed in claim 12, wherein:

said transistor includes a parasitic capacitance that is part of a matching network associated with said first configuration of said switchable network.

14. The duplexer claimed in claim 9, wherein:

said fist interconnect includes a first pass gate to controllably couple said first transmitter terminal to said first receiver terminal, said first pass gate including a PMOS device and an NMOS device.

15. The duplexer claimed in claim 9, wherein:

said at least one switch includes a transistor having first and second output terminals, said first output terminal being coupled to said first antenna terminal through a first circuit element and said second output terminal being coupled to said second antenna terminal through a second circuit element, said first and second circuit elements having a first element type.

16. The duplexer claimed in claim 15, wherein:

said switchable network includes a third circuit element connected between said first receiver terminal and said first antenna terminal and a fourth circuit element connected between said second receiver terminal and said second antenna terminal, said third and fourth circuit elements having a second element type, wherein said second element type is different from said first element type.

17. The duplexer claimed in claim 16, wherein:

said first and second circuit elements are capacitors and said third and fourth circuit elements are inductors.

18. The duplexer claimed in claim 9, wherein:

said at least one switch includes a transistor for changing said switchable network between said first and second configurations, said transistor changing said switchable network to said first configuration during a receive operation and said transistor changing said switchable network to said second configuration during a transmit operation, said transistor being located at a virtual ground.

19. A transceiver comprising:

a transmitter;

a receiver; and

a duplexer to allow said transmitter and said receiver to share a common antenna, said duplexer including;

an antenna port to connect the duplexer to an antenna;

a receiver port to connect the duplexer to said receiver;

a transmitter port to connect the duplexer to said transmitter;

an interconnect to couple said transmitter port to said receiver port; and

a reconfigurable network coup led to said antenna port, said receiver port and said transmitter port, said reconfigurable network to provide an impedance matching circuit between said antenna and said receiver during a receive operation and to provide an impedance transformation circuit between said antenna and said receiver during a transmit operation, said impedance transformation circuit comprising an inductor coupled to a capacitor and said impedance matching circuit comprising the inductor coupled to the capacitor that is removed from the reconfigurable network.

20. The transceiver claimed in claim 19, wherein:

said receiver port and said transmitter port of said duplexer each include first and second differential terminals.

21. The transceiver claimed in claim 19 wherein:

said transmitter, said receiver, and said duplexer are all implemented on a common semiconductor chip.

22. The transceiver claimed in claim 21 wherein:

said transmitter, said receiver, and said duplexer are implemented on said common semiconductor chip using VLSI techniques.

23. The transceiver claimed in claim 21 wherein:

said transmitter, said receiver, and said duplexer are implemented on said common semiconductor chip using CMOS structures.

24. The transceiver claimed in claim 21 comprising:

digital control circuitry for controlling the operation of said transceiver, said digital control circuitry being implemented on said common semiconductor chip with said transmitter, said receiver, and said duplexer.

25. The transceiver claimed in claim 21 comprising:

signal processing circuitry for processing receive data from said receiver, said signal processing circuitry being implemented on said common semiconductor chip with said transmitter, said receiver, and said duplexer.