Integrated memory

• US 6,728,143 B2
• Filed: 05/20/2002
• Issued: 04/27/2004
• Est. Priority Date: 05/18/2001
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Feurle, Robert
• Primary Examiner(s): Tran, M.
• Application Number:
  US10/151,088
• Publication Number:
  US 20020172085A1
• Time in Patent Office: 708 Days
• Field of Search: 365/191, 365/193
• US Class Current: 365/191
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

An integrated memory having a memory cell array has a control circuit for controlling a memory access for reading out or writing a data signal of one of the memory cells. The control circuit receives, for a memory access, an access command in the form of an activation command, a read command or a write command. Furthermore, the control circuit is designed and can be operated in such a way that, for a memory access, a configuration value for a CAS latency and/or a configuration value for specifying a burst access is received in a combined manner with the access command. As a result, a mode register and a corresponding programming step for programming the register can be eliminated.

Claims

1. An integrated memory, comprising:

a memory cell array having memory cells; and

a control circuit for controlling a memory access selected from the group consisting of a read memory access for reading out a data signal from one of said memory cells and a write memory access for writing a data signal into one of said memory cells;

for performing the memory access, said control circuit designed for receiving an access command selected from the group consisting of an activation command, a read command, and a write command;

for performing the memory access, said control circuit designed for receiving a configuration value in a combined manner with the access command; and

the configuration value being selected from the group consisting of a CAS latency value and a value for specifying a burst access.

2. The integrated memory according to claim 1, wherein:

said control circuit is designed to receive a multi-bit signal that includes the access command and the configuration value.

3. The integrated memory according to claim 2, comprising:

command pins for receiving the access command and for receiving the configuration value;

said command pins connected to said control circuit.

4. The integrated memory according to claim 1, comprising:

command pins for receiving the access command and for receiving the configuration value;

said command pins connected to said control circuit.

5. The integrated memory according to claim 1, wherein:

the configuration value is the value for specifying the burst access; and

the configuration value is selected from the group consisting of a value for specifying a burst length and a value for specifying a burst type.

6. The integrated memory according to claim 1, comprising:

address pins for transferring address signals for the memory access;

said address pins being not capable of transferring the configuration value.

7. The integrated memory according to claim 1, comprising:

address pins for transferring address signals for the memory access;

said address pins not being used for transferring the configuration value.