Integrated memory

  • US 6,728,143 B2
  • Filed: 05/20/2002
  • Issued: 04/27/2004
  • Est. Priority Date: 05/18/2001
  • Status: Active Grant
First Claim
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1. An integrated memory, comprising:

  • a memory cell array having memory cells; and

    a control circuit for controlling a memory access selected from the group consisting of a read memory access for reading out a data signal from one of said memory cells and a write memory access for writing a data signal into one of said memory cells;

    for performing the memory access, said control circuit designed for receiving an access command selected from the group consisting of an activation command, a read command, and a write command;

    for performing the memory access, said control circuit designed for receiving a configuration value in a combined manner with the access command; and

    the configuration value being selected from the group consisting of a CAS latency value and a value for specifying a burst access.

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