Salicided gate for virtual ground arrays

• US 6,730,564 B1
• Filed: 08/12/2002
• Issued: 05/04/2004
• Est. Priority Date: 08/12/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: FASL LLC
• Inventors: Ramsbey, Mark T., Sun, Yu, Chang, Chi, Shiraiwa, Hidehiko
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US10/217,821
• Time in Patent Office: 631 Days
• Field of Search: 438/257-267
• US Class Current: 438/258
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 438/954 Making oxide-nitride-oxide device

Abstract

The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.

Claims

1. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate having a core region and a peripheral region;

over the core region, forming a multilayer charge trapping dielectric;

forming a poly layer over at least the multilayer charge trapping dielectric; and

while at least a layer of the multilayer charge trapping dielectric in the core region has not been patterned, saliciding the poly layer in the core region.

2. The method of claim 1, further comprising pattering core region gates after siliciding the poly layer.

3. The method of claim 1, wherein the semiconductor substrate is provided without oxide islands in the core region.

4. The method of claim 3, wherein oxide islands are not formed in the core region.

5. The method of claim 4, further comprising:

forming at least one gate oxide layer over the peripheral region prior to forming the poly layer;

forming the poly layer over the gate oxide layer, as well as over the dielectric layers;

prior to saliciding, patterning peripheral region gates comprising the gate oxide layer and the poly layer; and

prior to saliciding, doping the substrate to form source and drain regions adjacent the peripheral region gates.

6. The method of claim 5, wherein the source and drain regions adjacent the peripheral region gates are salicided at the same time as the poly layer in the core region.

7. The method of claim 5, wherein the semiconductor substrate is provided without oxide islands in the core region.

8. The method of claim 6, wherein oxide islands are not formed in the core region.

9. The method of claim 1, wherein saliciding takes place prior to patterning the poly layer in the core region.

10. The method of claim 1, wherein saliciding takes place after patterning the poly layer in the core region.

11. The method of claim 1, wherein the virtual ground array non-volatile semiconductor memory device has a NOR device structure.

12. The method of claim 1, wherein the core region comprises buried bit lines.

13. The method of claim 1, wherein the semiconductor substrate comprises a silicon wafer.

14. The method of claim 1, wherein the poly layer comprises polysilicon.

15. A method of forming a virtual ground array non-volatile semiconductor memory device, comprising:

providing a semiconductor substrate having a core region and a peripheral region;

over the core region, forming a memory cell stack of which the topmost layer is a poly layer;

while the poly layer in the core region has not been patterned, saliciding the poly layer in the core region.

16. The method of claim 15, wherein the memory cell stack is a SONOS type memory cell stack.

17. The method of claim 16, wherein the virtual ground array non-volatile semiconductor memory device has a NOR device structure.

18. The method of claim 16, wherein the core region comprises buried bit lines.

19. The method of claim 16, wherein the virtual ground array non-volatile semiconductor memory device comprises a SONOS memory device.