Apparatus, methods and articles of manufacture for a low control voltage switch
First Claim
Patent Images
1. A switch comprising a plurality of field effect transistors (FETs) connected together in series, the plurality of FETs having six gates therebetween.
13 Assignments
0 Petitions
Accused Products
Abstract
A low control voltage switch utilizing a plurality of field effect transistors (FETs) having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. Feed-forward capacitors connected between the gate and source of an uppermost FET and the gate and drain of a lowermost FET are used to reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lower the harmonics of the switch.
46 Citations
41 Claims
- 1. A switch comprising a plurality of field effect transistors (FETs) connected together in series, the plurality of FETs having six gates therebetween.
-
28. A switch comprising:
-
a plurality of field effect transistors (FETs) connected together in series, each FET having a source, a drain and at least one gate, the plurality of FETs having a total of six gates therebetween;
a first feed-forward capacitor coupled between the source and the gate of a first FET of said plurality of FETs; and
a second feed-forward capacitor coupled between the drain and the gate of a last FET of said plurality of FETs. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
a gate resistance topology coupled between the six gates and a control voltage input; - and
a bypass resistance topology connected between the source of the first FET and the drain of the last FET.
-
-
39. A device having a plurality of switches in parallel to each other and tied to same source voltage input, each switch comprising:
-
a plurality of field effect transistors (FETs) connected together in series having a total of six gates therebetween, said plurality of FETs including an uppermost FET connecting to the source voltage input and a lowermost FET connecting to an output;
a first feed-forward capacitor coupled between a source and a gate of the uppermost FET; and
a second feed-forward capacitor coupled between a drain and a gate of the lowermost FET. - View Dependent Claims (40, 41)
-
Specification