Wafer-level coated copper stud bumps

• US 6,731,003 B2
• Filed: 03/11/2003
• Issued: 05/04/2004
• Est. Priority Date: 03/12/2002
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Tangpuz, Consuelo, Cruz, Erwin Victor R.
• Primary Examiner(s): Clark, Jasmine
• Application Number:
  US10/386,621
• Publication Number:
  US 20030173684A1
• Time in Patent Office: 420 Days
• Field of Search: 257/737, 257/738, 257/783, 228/180.22, 438/613
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method for forming a semiconductor die package is disclosed. In one embodiment, the method includes forming a semiconductor die comprising a semiconductor device. A plurality of copper bumps is formed on the semiconductor die using a plating process. An adhesion layer is formed on each of the copper bumps, and a noble metal layer is formed on each of the copper bumps.

Claims

1. A method comprising:

(a) forming a plurality of copper bumps on a semiconductor die using a plating process, wherein the semiconductor die comprises a semiconductor device;

(b) forming an adhesion layer on each copper bump in the plurality of copper bumps; and

(c) forming an oxidation resistant layer on each copper bump in the plurality of copper bumps, wherein the adhesion layer is between the oxidation resistant layer and the copper bump.

2. The method of claim 1 wherein the semiconductor device is a power MOSFET (metal oxide semiconductor field effect transistor).

3. The method of claim 1 wherein the oxidation resistant layer and the adhesion layer coat a top surface and a side surface of each copper bump.

4. The method of claim 1 wherein each copper bump has a thickness greater than about 25 microns.

5. The method of claim 1 wherein the semiconductor die is in a semiconductor wafer, and wherein the method further comprises:

dicing the semiconductor wafer to form individual semiconductor dies.

6. The method of claim 1 further comprising:

packaging the semiconductor die after (c).

7. The method of claim 1 wherein the oxidation resistant layer comprises a noble metal.

8. The method of claim 1 wherein the oxidation resistant layer comprises a noble metal, and wherein the noble metal comprises gold or a gold alloy.

9. A method comprising:

(a) forming a plurality of copper bumps on a semiconductor die using a plating process, wherein the semiconductor die comprises a semiconductor device;

(b) forming an adhesion layer comprising nickel on each copper bump in the plurality of copper bumps;

(c) forming an oxidation resistant layer comprising gold on each copper bump in the plurality of copper bumps, wherein the adhesion layer is between the oxidation resistant layer and the copper bump to form a coated copper bump; and

(d) bonding the coated copper bump to a conductive region of a circuit substrate using solder.

10. The method of claim 9 wherein the semiconductor device comprises a vertical power MOSFET.

11. A bumped semiconductor die comprising:

(a) a semiconductor die comprising a semiconductor device;

(b) a plated copper bump on the semiconductor die, the plated copper bump having a top surface;

(c) an adhesion layer on at least the top surface of the plated copper bump; and

(d) an oxidation resistant layer on the adhesion layer.

12. The bumped semiconductor die claim 11 wherein the semiconductor device is a power MOSFET (metal oxide field effect transistor).

13. The bumped semiconductor die of claim 11 wherein the plated copper bump is electroplated.

14. The bumped semiconductor die of claim 11 wherein the adhesion layer comprises nickel and wherein the oxidation resistant layer comprises gold.

15. The bumped semiconductor die of claim 11 wherein the oxidation resistant layer comprises a noble metal.

16. The bumped semiconductor die of claim 11 wherein the semiconductor die includes a source region and a gate region at one side of the semiconductor die and a drain region at an opposite side of the semiconductor die.

17. A semiconductor die package comprising the bumped semiconductor die of claim 11.