Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
First Claim
1. A memory device comprising:
- a plurality of memory arrays comprising a first memory array and a second memory array;
a first circuit structure disposed beneath the first memory array, wherein the first circuit structure comprises all of the circuits disposed beneath the first memory array; and
a second circuit structure, different from the first circuit structure, disposed beneath the second memory array, wherein the second circuit structure comprises all of the circuits disposed beneath the second memory array.
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Accused Products
Abstract
The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
93 Citations
51 Claims
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1. A memory device comprising:
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a plurality of memory arrays comprising a first memory array and a second memory array;
a first circuit structure disposed beneath the first memory array, wherein the first circuit structure comprises all of the circuits disposed beneath the first memory array; and
a second circuit structure, different from the first circuit structure, disposed beneath the second memory array, wherein the second circuit structure comprises all of the circuits disposed beneath the second memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device comprising:
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a plurality of memory arrays disposed above a substrate;
a first decoder circuit associated with and largely disposed beneath a first memory array and also associated with a second memory array; and
a second decoder circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein at least one of the plurality of row or column decoder circuits is associated with a memory array above its location and an adjacent memory array. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both;
wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
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43. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit;
wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
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44. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays;
wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
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45. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides;
wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
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46. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides;
wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.
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47. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both;
wherein the memory cells of the plurality of memory arrays comprise one of the following;
a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
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48. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit;
wherein the memory cells of the plurality of memory arrays comprise one of the following;
a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
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49. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays;
wherein the memory cells of the plurality of memory arrays comprise one of the following;
a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
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50. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides;
wherein the memory cells of the plurality of memory arrays comprise one of the following;
a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
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51. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides;
wherein the memory cells of the plurality of memory arrays comprise one of the following;
a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.
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Specification