Cross-bar matrix for connecting digital resources to I/O pins of an integrated circuit

• US 6,738,858 B1
• Filed: 05/31/2000
• Issued: 05/18/2004
• Est. Priority Date: 05/31/2000
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Labs CP, Inc. (Silicon Laboratories Incorporated)
• Inventors: Fernald, Kenneth W., Alfano, Donald E.
• Primary Examiner(s): Thai, Xuan M.
• Assistant Examiner(s): King, Justin
• Application Number:
  US09/583,260
• Time in Patent Office: 1,448 Days
• Field of Search: 710/317, 710/100, 710/305, 710/316, 712/11, 709/209, 708/404, 326/41
• US Class Current: 710/317
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/1325 Priority service
• CPC Class Codes: H04Q 3/52 using static devices in switching stages, e.g. electronic switching arrangements

Abstract

A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Claims

1. A circuit for assigning digital resources to pins of an integrated circuit, comprising:

a plurality of the pins of said integrated circuit;

a microprocessor formed in said integrated circuit;

a plurality of selectable digital resources formed in said integrated circuit, each of said digital resources having at least two interface signal paths that require interface to at least two of said plurality of pins that are selected; and

a cross-bar matrix having a plurality of signal inputs coupled respectively to the at least two interface signal paths of select ones of said digital resources, and a plurality of signal outputs coupled to the pins of said integrated circuit, said cross-bar matrix controlled by said microprocessor for selectively coupling said ones of said signal inputs to different said signal outputs, whereby the at least two interface signal paths of select ones of said digital resources can be coupled to different ones of said plurality of pins under control of said microprocessor.

2. The circuit of claim 1, wherein said cross-bar matrix includes a plurality of cells, each said cell being identically constructed.

3. The circuit of claim 1, wherein said cross-bar matrix is constructed with a plurality of rows associated with said signal inputs, and with a plurality of columns associated with said signal outputs, and each cell of the row is controlled by said microprocessor for coupling or not coupling the digital resource at the respective signal input to the signal output.

4. The circuit of claim 3, wherein each said cell is individually controlled by said microprocessor.

5. The circuit of claim 3, wherein each row of said cross-bar matrix includes a register with a plurality of outputs, each said register output controlling operation of the respective cell in the row.

6. The circuit of claim 1, wherein each said row is associated with a signal output to the digital resources, and each said column is associated with a signal input from the respective pin, whereby said cross-bar matrix is adapted for coupling signals therethrough in a bidirectional manner.

7. The circuit of claim 6, wherein said microprocessor is programmed to control whether said pins are configured as input pins or as output pins.

8. The circuit of claim 7, further including a control signal generated by said microprocessor and coupled through said cross-bar matrix for controlling whether one of said plurality of pins is to be configured as the input pin or as the output pin.

9. The circuit of claim 8, further including a pin driver circuit for providing input/output circuit functions with regard to each of said plurality of pins.

10. A cross-bar matrix, comprising:

a plurality of matrix cells arranged in rows and columns, each said row of cells associated with a common signal input from a digital resource, which said digital resource is has at least two interface signal paths that are required to be coupled to at least two of said rows of cells, and each column of cells associated with a common signal output; and

each said cell having a control input for controlling whether the cell is to couple a signal on the associated common signal input to the common signal output associated with the cell, whereby any input signal of the row can be coupled to any signal output with the coupling being such that the grouping of signal outputs is functionally associated with said digital resource.

11. The cross-bar matrix of claim 10, wherein each said cell of the row is coupled to a data signal line for receiving the same data signal, and each cell in a row is coupled to a different control line for controlling whether the cells in the row are to couple the data signal to the respective common signal output.

12. The cross-bar matrix of claim 11, wherein said control lines are coupled to a respective circuit associated with each row, and said circuit is operative to enable only one control line per row at a time.

13. The cross-bar matrix of claim 11, wherein each cell of the row is coupled to an output enable signal line for receiving an output enable signal from the digital resource, and said control line controls whether the cells in the row are to couple the output enable signal to the respective common signal output.

14. The cross-bar matrix of claim 11, wherein each said cell of the column has a data signal output coupled to a logic circuit for providing a single output corresponding to a selected cell of the column.

15. The cross-bar matrix of claim 11, further including an enable circuit coupled between a logic circuit and a pin associated with the respective column, said enable circuit being controlled to enable or disable said data signals from being coupled to said respective pin.

16. The cross-bar matrix of claim 11, wherein each cell in the row includes a circuit for receiving a data signal from a pin associated with the respective column, and said control line controls whether said data receiving circuit is to couple received data from said matrix to the digital resource.

17. The cross-bar matrix of claim 16, wherein each cell of the row includes a data receive output line coupled to a logic circuit, said logic circuit providing a single output to the digital resource of the cell in the row that was enabled by said control line.

18. A cross-bar matrix, comprising:

a plurality of cells arranged in rows and columns, each cell in the row associated with a common data signal, and each cell in the row associated with a common output enable signal, and each cell in the column associated with a common I/O pin;

each cell in the row receiving a different enable signal for enabling the respective cell to couple the data signal and the output enable signal to the respective I/O pin,

each cell in the row including a data signal circuit responsive to the enable signal for coupling therethrough the data signal, and each cell in the row including an output enable signal circuit responsive to the enable signal for coupling therethrough the output enable signal; and

each cell in the row including a data receive circuit for receiving the data signal from the respective I/O pin, and responsive to said enable signal for coupling the data receive signal from the I/O pin to a data resource wherein said data resource has at least two interface signal paths that require coupling to at least two respective ones of said I/O pins, such that I/O pins can be grouped with an associated said data resource.

19. The cross-bar matrix of claim 18, wherein each cell of said matrix is identically constructed.

20. The cross-bar matrix of claim 18, further in combination a microprocessor formed in an integrated circuit with said cross-bar matrix, and said microprocessor controlling operation of the cells of said cross-bar matrix.