Integrated circuits and methods for their fabrication

• US 6,740,582 B2
• Filed: 04/26/2002
• Issued: 05/25/2004
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Siniaguine, Oleg
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US10/133,595
• Publication Number:
  US 20020127868A1
• Time in Patent Office: 760 Days
• Field of Search: 438/637-639, 438/459, 257/621-622
• US Class Current: 438/637
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.

Claims

1. A method for fabricating an integrated circuit, the method comprising:

(a) providing a body having one or more openings in a first side;

(b) fabricating a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the body by the first dielectric;

(c) removing material of the body from a second side of the body to expose the first dielectric on the second side, wherein when the first dielectric becomes exposed on the second side, the first dielectric covers the conductor on the second side so that the conductor is not exposed on the second side;

(d) after the first dielectric has been exposed on the second side, removing the material of the body and the first dielectric from the second side to expose the conductor in each of the openings, wherein the removing of the material of the body and the first dielectric comprises a process in which the removal rate of the first dielectric is lower than the removal rate of material of the body;

wherein the body comprises a transistor and/or a capacitor.

2. The method of claim 1 wherein in said process the removal rate of the first dielectric is about 10 times lower than the removal rate of the material of the body.

3. The method of claim 1 wherein removing material from the second side comprises plasma etching of the second side of the body at about an atmospheric pressure as the body is held in a non-contact holder.

4. The method of claim 1 wherein the body comprises semiconductor material.

5. The method of claim 1 further comprising, after the removal of the material from the second side, connecting at least one integrated circuit of the body to one or more other integrated circuits to form a vertical integrated circuit, with at least one of the exposed conductors contacting a contact pad of another integrated circuit.

6. The method of claim 1 wherein said process removes at least a substantial portion of the total amount of the first dielectric removed in the operation (d).

7. The method of claim 1 wherein all of the first dielectric removed in the operation (d) is removed simultaneously with removal of material of the body but at a lower rate than the material of the body.

8. The method of claim 1 wherein all of the first dielectric removed in the operation (d) is removed simultaneously with removal of semiconductor material of the body but at a lower removal rate than the semiconductor material of the body.

9. The method of claim 8 wherein the semiconductor material is silicon.

10. The method of claim 1 wherein the first dielectric in each of said openings, when viewed from the second side, is laterally surrounded by semiconductor material of the body, and

when the first dielectric is being removed in each of said openings to expose the conductor from the second side, the laterally surrounding semiconductor material of the body is being removed simultaneously and at a faster rate than the first dielectric.

11. The method of claim 1 wherein removing the first dielectric at a lower rate than the material of the body improves electrical insulation between the conductor in each of said openings and the body.

12. The method of claim 1 further comprising attaching at least one conductor exposed on the second side to another conductor with solder, wherein the first dielectric protrudes from the second side around the exposed conductor and improves electrical insulation between the solder and the body.

13. The method of claim 1 wherein the operation (d) is an unmasked etch removing all of the material exposed on the second side at least until the conductor is exposed in each of the openings.

14. The method of claim 1 wherein after the conductor in each of the openings is exposed, said process continues to remove the material of the body and, at the same time, to remove the first dielectric at a lower rate than the material of the body.

15. The method of claim 1 wherein at the conclusion of the operation (d) the conductor protrudes from the second side at each of the openings.