CAM cells and differential sense circuits for content addressable memory (CAM)

• US 6,744,653 B1
• Filed: 07/24/2002
• Issued: 06/01/2004
• Est. Priority Date: 10/04/2001
• Status: Expired due to Term

• Current Assignee: Xiaohua Huang
• Original Assignee: Xiaohua Huang
• Inventors: Huang, Xiaohua
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): HUR, JUNG H
• Application Number:
  US10/202,621
• Time in Patent Office: 678 Days
• Field of Search: 365/49, 365/207, 365/210, 711/108
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A dummy content-addressable memory (CAM) cell and a dummy ternary CAM cell are connected to each row in a CAM and a ternary CAM array, respectively, to enable a differential match line sensing based on the content stored. The ternary CAM cell is for a differential match line sensing in low power applications. A method includes generating a voltage difference between a match line signal and a reference line signal, and then detecting and amplifying the voltage difference to determine a match or a mismatch.

Claims

1. A content addressable memory (CAM) cell comprising:

a memory cell operable to store a bit value; and

a comparison circuit coupled to the memory cell and configured to detect the bit value stored in the memory cell, the comparison circuit including

an output transistor coupled to a match line and configured to provide a drive for the match line based on the detected bit value, and

a dummy transistor coupled to a dummny line and configured to provide a drive for the dummy line based on an inverted detected bit value, wherein the match line and dummy line are used to detect output values provided by other CAM cells also coupled to the match and dummy lines.

2. The CAM cell of claim 1, wherein the comparison circuit further includes

a first pair of transistors configured to receive the detected bit value and provide a drive for the output transistor, and

a second pair of transistors configured to receive the inverted detected bit value and provide a drive for the dummy transistor.

3. The CAM cell of claim 1, wherein the dummy transistor has a smaller dimension and less current flowing through than the output transistor and is located in close proximity to the output transistor.

4. The CAM cell of claim 3, wherein the dummy transistor is approximately half the dimension of the output transistor and is turned ON during sensing operation.

5. A content addressable memory (CAM) cell comprising:

a memory cell operable to store a data bit value;

a secondary cell operable to store a control bit value and a complementary control bit value; and

a comparison circuit coupled to the memory cell and the secondary cell and configured to detect the data bit value stored in the memory cell and the control bit value and the complementary control bit value stored in the secondary cell, the comparison circuit including

a pair of output transistors coupled to a match line and configured to provide a drive for the match line based on the detected data bit value and the detected control bit value, and

a pair of dummy transistors coupled to a dummy line and configured to provide a drive for the dummy line based on the detected control bit value and the detected complementary control bit value,

wherein the match line and the dummy line are used to detect an output value provided by the CAM cell.

6. The CAM cell of claim 5, wherein the dummy transistors have similar dimensions and orientation as the output transistors and located in close proximity to the output transistors.

7. The CAM cell of claim 5, wherein an output of the pair of dummy transistors are OFF during sensing operation.

8. A content addressable memory (CAM) cell comprising:

a memory cell operable to store a data bit value;

a secondary cell operable to store a control bit value; and

a comparison circuit coupled to the memory cell and the secondary cell and configured to detect the data bit value stored in the memory cell and the control bit value stored in the secondary cell, the comparison circuit including

a pair of output transistors coupled to a match line and configured to provide a drive for the match line based on the detected data bit value and the detected control bit value, and

a pair of dummy transistors coupled to a dummy line and configured to provide a drive for the dummy line based on an inverted detected data bit value and the detected control bit value.

9. The CAM cell of claim 8, wherein the comparison circuit further includes

a first pair of transistors configured to receive the detected data bit value and provide a drive for a first output transistor, and

a second pair of transistors configured to receive the inverted detected bit value and provide a drive for a first dummy transistor.

10. The CAM cell of claim 8, wherein the dummy transistors have smaller dimension and less current flowing through than the output transistors, are located in close proximity to the output transistors, and are turned ON during sensing operation.

11. The CAM cell of claim 10, wherein the dummy transistors are approximately half the dimension of the output transistors.

12. A sense circuit for sensing a logic state of a match line in a content addressable memory (CAM), comprising:

a plurality of dummy transistors operative to provide a reference signal;

a first amplifier having an input operatively coupled to the match line, wherein the match line is coupled to a plurality of output transistors for a plurality of CAM cells, each output transistor providing an output value indicative of a comparison result for a respective CAM cell; and

a second amplifier having an input configured to receive the reference signal, wherein the first and second amplifiers are coupled in a positive feedback configuration and operative to amplify a difference between a signal on the match line and the reference signal,

wherein the plurality of output transistors are N-channel transistors having drains that couple to the match line and sources that couple to a first common line, and wherein the input of the first amplifier is coupled to the first common line.

13. The sense circuit of claim 12, wherein the plurality of dummy transistors are N-channel transistors having drains that couple to a dummy line and sources that couple to a second common line, and wherein the input of the second amplifier is coupled to the second common line.

14. The sense circuit of claim 13, wherein the match line and the dummy line are pre-charged prior to being sensed by the sense circuit.

15. A sense circuit for sensing a logic state of a match line in a content addressable memory (CAM), comprising:

a plurality of dummy transistors operative to provide a reference signal;

a first amplifier having an input operatively coupled to the match line, wherein the match line is coupled to a plurality of pairs of output transistors for a plurality of CAM cells, each pair of output transistors providing an output value indicative of a comparison result for a respective CAM cell; and

a second amplifier having an input configured to receive the reference signal, wherein the first and second amplifiers are coupled in a positive feedback configuration and operative to amplify a difference between a signal on the match line and the reference signal,

wherein each pair of output transistors comprises a pair of series-coupled N-channel transistors having one drain coupled to the match line and one source coupled to a first common line, and wherein the input of the first amplifier is coupled to the first common line.

16. The sense circuit of claim 15, wherein the plurality of dummy transistors comprise a plurality of pairs of series-coupled N-channel dummy transistors, each pair of dummy transistors having one drain coupled to a dummy line and one source coupled to a second common line, and wherein the input of the second amplifier is coupled to the second common line.

17. A method for sensing a logic state of a match line in a content addressable memory (CAM), comprising:

sensing a signal on a first common line, wherein the signal on the first common line is related to a signal on the match line;

providing a reference signal on a second common line based on a plurality of dummy transistors;

determining a difference between the sensed signal on the first common line and the reference signal on the second common line;

amplifying the determined difference with a positive feedback amplifier; and

providing an output value indicative of the logic state of the match line based on the amplified difference.