Serial interface for reprogramming multiple network interface cards and method of operation

• US 6,745,325 B1
• Filed: 11/15/2000
• Issued: 06/01/2004
• Est. Priority Date: 11/15/2000
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Gavlik, John E.
• Primary Examiner(s): Butler, Dennis M.
• Assistant Examiner(s): Suryawanshi, Suresh K
• Application Number:
  US09/713,542
• Time in Patent Office: 1,294 Days
• Field of Search: 713/100, 713/1, 709/221, 709/242, 709/220, 714/4
• US Class Current: 713/100
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

There is disclosed, for use in a communication device comprising a plurality of network interface cards for communicating with an external data network, an apparatus for simultaneously transferring a replacement program into a plurality of dedicated memories in the plurality of network interface cards. The apparatus comprises: 1) a replacement program memory for storing the replacement program; 2) a first microcontroller coupled to the replacement program memory and having a first dedicated memory associated therewith; and 3) a second microcontroller coupled to the replacement program memory and having a second dedicated memory associated therewith. After a power reset has occurred, the first microcontroller monitors a first signal line to the replacement program memory to determine if the second microcontroller is transferring the replacement program from the replacement program memory to the second dedicated memory and wherein the first microcontroller, in response to a determination that the second microcontroller is transferring the replacement program, transfers at least a portion of the replacement program to the first dedicated memory as the replacement program is read from the replacement program memory by the second microcontroller.

Claims

1. For use in a communication device comprising a plurality of network interface cards for communicating with an external data network, an apparatus for simultaneously transferring a replacement program into a plurality of dedicated memories in said plurality of network interface cards, said apparatus comprising:

a replacement program memory capable of storing said replacement program;

a first microcontroller coupled to said replacement program memory and having a first dedicated memory associated therewith;

a second microcontroller coupled to said replacement program memory and having a second dedicated memory associated therewith,

wherein, after a power reset has occurred, said first microcontroller monitors a first signal line to said replacement program memory to determine if said second microcontroller is transferring said replacement program from said replacement program memory to said second dedicated memory and wherein said first microcontroller, in response to a determination that said second microcontroller is transferring said replacement program, transfers at least a portion of said replacement program to said first dedicated memory as said replacement program is read from said replacement program memory by said second microcontroller.

2. The apparatus as set forth in claim 1 wherein said first microcontroller monitors said first signal line for a first predetermined period of time to determine if said second microcontroller is transferring said replacement program.

3. The apparatus as set forth in claim 2 wherein said first microcontroller, at an expiration of said first predetermined period of time and in response to a determination that said second microcontroller is not transferring said replacement program, transfers said replacement program from said replacement program memory to said first dedicated memory.

4. The apparatus as set forth in claim 3 wherein a length of said first predetermined period of time is determined by a fixed address applied by a resistor matrix to address pins of said first microcontroller.

5. The apparatus as set forth in claim 4 wherein said replacement program memory comprises a serial electronically erasable programmable read only memory (EEPROM).

6. The apparatus as set forth in claim 5 wherein serial EEPROM is coupled to said first and second microcontrollers by a serial data line and a serial clock line.

7. The apparatus as set forth in claim 6 wherein said serial data line and a serial clock line are used to transfer said replacement program from said replacement program memory to said first and second dedicated memories.

8. The apparatus as set forth in claim 1 wherein, after a power reset has occurred, said second microcontroller monitors said first signal line to said replacement program memory to determine if said first microcontroller is transferring said replacement program from said replacement program memory to said first dedicated memory and wherein said second microcontroller, in response to a determination that said first microcontroller is transferring said replacement program, transfers at least a portion of said replacement program to said second dedicated memory as said replacement program is read from said replacement program memory by said first microcontroller.

9. The apparatus as set forth in claim 8 wherein said second microcontroller monitors said first signal line for a second predetermined period of time to determine if said first microcontroller is transferring said replacement program.

10. The apparatus as set forth in claim 9 wherein said second microcontroller, at an expiration of said second predetermined period of time and in response to a determination that said first microcontroller is not transferring said replacement program, transfers said replacement program from said replacement program memory to said second dedicated memory.

11. A switch capable of communicating with a data network comprising:

a plurality of network interface cards, each of said plurality of network interface cards having an external interface for communicating with said external data network;

a switch matrix coupled to an internal interface of each of said plurality of interface cards and capable of transmitting data therebetween;

an apparatus for simultaneously transferring a replacement program into a plurality of dedicated memories in said plurality of network interface cards, said apparatus comprising;

a replacement program memory capable of storing said replacement program;

a first microcontroller coupled to said replacement program memory and having a first dedicated memory associated therewith;

a second microcontroller coupled to said replacement program memory and having a second dedicated memory associated therewith,

wherein, after a power reset has occurred, said first microcontroller monitors a first signal line to said replacement program memory to determine if said second microcontroller is transferring said replacement program from said replacement program memory to said second dedicated memory and wherein said first microcontroller, in response to a determination that said second microcontroller is transferring said replacement program, transfers at least a portion of said replacement program to said first dedicated memory as said replacement program is read from said replacement program memory by said second microcontroller.

12. The switch as set forth in claim 11 wherein said first microcontroller monitors said first signal line for a first predetermined period of time to determine if said second microcontroller is transferring said replacement program.

13. The switch as set forth in claim 12 wherein said first microcontroller, at an expiration of said first predetermined period of time and in response to a determination that said second microcontroller is not transferring said replacement program, transfers said replacement program from said replacement program memory to said first dedicated memory.

14. The switch as set forth in claim 13 wherein a length of said first predetermined period of time is determined by a fixed address applied by a resistor matrix to address pins of said first microcontroller.

15. The switch as set forth in claim 14 wherein said replacement program memory comprises a serial electronically erasable programmable read only memory (EEPROM).

16. The switch as set forth in claim 15 wherein serial EEPROM is coupled to said first and second microcontrollers by a serial data line and a serial clock line.

17. The switch as set forth in claim 16 wherein said serial data line and a serial clock line are used to transfer said replacement program from said replacement program memory to said first and second dedicated memories.

18. The switch as set forth in claim 11 wherein, after a power reset has occurred, said second microcontroller monitors said first signal line to said replacement program memory to determine if said first microcontroller is transferring said replacement program from said replacement program memory to said first dedicated memory and wherein said second microcontroller, in response to a determination that said first microcontroller is transferring said replacement program, transfers at least a portion of said replacement program to said second dedicated memory as said replacement program is read from said replacement program memory by said first microcontroller.

19. The switch as set forth in claim 18 wherein said second microcontroller monitors said first signal line for a second predetermined period of time to determine if said first microcontroller is transferring said replacement program.

20. The switch as set forth in claim 19 wherein said second microcontroller, at an expiration of said second predetermined period of time and in response to a determination that said first microcontroller is not transferring said replacement program, transfers said replacement program from said replacement program memory to said second dedicated memory.