Semiconductor device with DRAM inside

CAFC
  • US 6,747,320 B2
  • Filed: 07/18/2003
  • Issued: 06/08/2004
  • Est. Priority Date: 08/07/2002
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising a DRAM region and a high-speed CMOS logic region that are co-resident with each other,wherein a pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM are disposed respectively in one active region in parallel to each other in the same direction as that of bit lines, and a pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors are isolated by shallow trench isolation (STI) regions.

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