System for simplifying the programmable memory to logic interface in FPGA

  • US 6,748,577 B2
  • Filed: 06/28/2002
  • Issued: 06/08/2004
  • Est. Priority Date: 06/29/2001
  • Status: Active Grant
First Claim
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1. A programmable a gate array (PGA) comprising:

  • at least one embedded memory having a plurality of address lines, data lines, and control lines connected thereto;

    a plurality of programmable logic blocks (PLBs);

    a plurality of input/outputs (I/Os);

    a plurality of routing lines interconnecting said at least one embedded memory, said PLBs, and said I/Os;

    an interface for isolating the routing lines from said address lines, data lines, and control lines; and

    a plurality of dedicated connections for connecting said PLBs and said I/Os to said at least one embedded memory.

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