Lock in pinned photodiode photodetector

• US 6,750,485 B2
• Filed: 06/12/2003
• Issued: 06/15/2004
• Est. Priority Date: 08/19/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Krymski, Alexander, Fossum, Eric R., Berezin, Vladimir
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Dao H.
• Application Number:
  US10/459,595
• Publication Number:
  US 20030213984A1
• Time in Patent Office: 369 Days
• Field of Search: 257/232, 257/233, 257/247, 257/292
• US Class Current: 257/232
• CPC Class Codes: G01S 7/487 Extracting wanted echo signals , e.g. pulse detection
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.

Claims

1. A system, comprising:

a pinned photodiode having a photodiode area;

a plurality of gates, each of said plurality of gates having one end coupled to said photodiode area; and

a plurality of photocarrier integrator elements, each of said photocarrier integrator elements coupled to the other end of each of said plurality of gates.

2. The system as in claim 1, further comprising a control input on each of said plurality of gates, enabling connection of a respective photocarrier integrator element to said photodiode area.

3. The system as in claim 2, further comprising a controller element which drives said control input controlling said plurality of gates such that no more than one of said control element is active at any time.

4. The system as in claim 3, wherein there are four of said photocarrier integrator elements, and wherein said controller element successively enables a first photocarrier integrator to accumulate carrier between a time 0 to π

/2, a second photocarrier integrator to accumulate carriers between a time π

/2 and π

;

a third photocarrier integrator to accumulate carriers between a time π and

3π

/2, and a fourth photocarrier integrator to accumulate carriers between a time 3π

/2 and 2π

.