Method and apparatus for synchronizing data transmission and reception over a network

• US 6,754,295 B1
• Filed: 04/07/2000
• Issued: 06/22/2004
• Est. Priority Date: 04/07/2000
• Status: Expired due to Fees

• Current Assignee: Comrex Corp
• Original Assignee: Comrex Corp
• Inventors: Hartnett, Thomas
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): ODOM, CURTIS B
• Application Number:
  US09/545,375
• Time in Patent Office: 1,537 Days
• Field of Search: 375/222, 375/376, 375/355, 375/356, 380/274, 379/399.01, 379/352, 370/352
• US Class Current: 375/356
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06

Abstract

In one embodiment, the invention is directed to methods and system for converting an analog signal to digital samples for transmission over a communication network, and for converting digital samples received over a communication network to an analog signal. According to one feature, the system of the invention generates encoding and decoding master clocks from local oscillators, thus enabling the system of the invention to operate in environments where reliable timing signal are not available from the communication network. According to another feature, the system of the invention adjusts the frequencies of the encoding and decoding master clocks based on a connect rate to the communication network. In a further feature, the system of the invention employs encoding and decoding buffers for buffering the digital samples between a modem or a digital network access device, and signal converters to maintain a defined time relationship between digital samples being transferred between the modem or the digital network access device and the signal converters.

Claims

1. A method for converting an analog signal to a digital signal for transmission over a communication network, said method comprising,

communicatively connecting to said communication network through a network interface, wherein said network interface is one of a modem or a digital network access device,

detecting a connect rate between said network interface and said communication network,

providing a local oscillator operating independently of said communication network,

generating an encoding master clock signal from said local oscillator, wherein said encoding master clock signal operates at a substantially stable frequency that depends at least in part on said connect rate,

receiving an analog signal,

converting said analog signal into digital samples using an analog-to-digital converter operating at a selected sampling rate, wherein said selected sampling rate is related to said frequency of said encoding master clock signal,

transferring said digital samples from said analog-to-digital converter to said network interface for output onto said communication network, and when transferring said digital samples from said analog-to-digital converter to said network interface, intermediately storing said digital samples in an encoding buffer having a plurality of locations,

maintaining a defined time relationship between each of said digital samples while said digital samples are being transferred between said analog-digital-converter and said network interface,

providing a fill pointer associated with said encoding buffer, wherein said fill pointer points to one of the locations in said encoding buffer and indicates to which of the locations an incoming one of said digital samples is to be stored,

incrementing said fill pointer to point to a next fill one of said locations subsequent to storing one of said digital samples in said encoding buffer,

resetting said fill pointer to point to a first location in said encoding buffer in response to storing one of said digital samples in a last location of said encoding buffer,

providing an empty pointer associated with said encoding buffer, wherein said empty pointer points to one of the locations in said encoding buffer storing one of said digital samples to be transferred to said network interface for output,

incrementing said empty pointer to point to a next transfer one of the locations containing a next one of said digital samples to be transferred to said network interface, and

resetting said empty pointer to point to said first location in said encoding buffer in response to transferring one of said digital samples from said last location of said encoding buffer to said network interface.

2. A method according to claim 1 further comprising, monitoring a distance between said fill pointer and said empty pointer, wherein said distance is measured in relation to a number of locations between a location pointed to by said fill pointer and a location pointed to by said empty pointer.

3. A method according to claim 2 further comprising, decreasing said selected sampling rate in response to said distance becoming less than a predefined closeness threshold.

4. A method according to claim 2 further comprising, increasing said selected sampling rate in response to said distance becoming greater than a predefined separation threshold.

5. A method according to claim 2 further comprising, decreasing said frequency of said encoding master clock signal in response to said distance becoming less than a predefined closeness threshold.

6. A method according to claim 5 further comprising, decreasing said sampling rate in dependence on said decreasing of said frequency of said encoding master clock.

7. A method according to claim 2 further comprising, increasing said frequency of said encoding master clock signal in response to said distance becoming greater than a predefined separation threshold.

8. A method according to claim 7 further comprising, increasing said sampling rate in dependence on said increasing of frequency of said encoding master clock signal.

9. A method according to claim 1, wherein said generating of said encoding master clock signal further comprises,

frequency dividing a clock signal from said local oscillator to obtain a phase comparator reference signal,

determining an initial divide ratio for performing said frequency dividing based at least in part on said connect rate, and

phase locking said comparator reference signal to provide said encoding master clock signal at a substantially constant initial frequency.

10. A method according to claim 2, wherein generating a master clock signal further comprises,

frequency dividing a clock signal from said local oscillator to obtain a phase comparator reference signal,

determining an initial divide ratio for performing said frequency dividing based at least in part on said connect rate, and

phase locking said comparator reference signal to provide said encoding master clock signal at said substantially stable frequency.

11. A method according to claim 10 further comprising,

adjusting said substantially stable frequency in dependence on said distance between said fill pointer and said empty pointer.

23. The method of claim 1 further comprising adjusting said frequency of said master clock to maintain said defined time relationship.

24. The method of claim 1 further comprising adjusting said sampling rate of said analog-to-digital converter to maintain said defined time relationship.

12. A method for converting digital samples received over a communication network to an analog signal, said method comprising,

communicatively connecting to said communication network through a network interface, wherein said network interface is one of a modem and a digital network access device,

detecting a connect rate between said network interface and said communication network,

providing a local oscillator operating independently of said communication network,

generating a decoding master clock signal from said local oscillator, wherein said decoding master clock signal operates at a substantially stable frequency that depends at least in part on said connect rate,

receiving digital samples from said communication network by way of said network interface,

operating a digital-to-analog converter at a selected conversion rate, wherein said selected conversion rate is related to said substantially stable frequency of said encoding master clock signal,

transferring said digital samples from said network interface to said digital-to-analog converter, and when transferring said digital samples from said network interface to said digital-to-analog converter, intermediately storing said digital samples in a decoding buffer having a plurality of locations,

converting said digital samples to an analog signal at said digital-to-analog converter,

maintaining a defined time relationship between each of said digital samples while said digital samples are being transferred between said network interface and said digital-to-analog converter,

providing a fill pointer associated with said decoding buffer, wherein said fill pointer points to one of the locations in said decoding buffer and indicates to which of the locations an incoming one of said digital samples is to be stored,

incrementing said fill pointer to point to next fill one of said locations subsequent to storing one of said digital samples in said decoding buffer,

resetting said fill pointer to point to a first location in said buffer in response to storing one of said digital samples in a last location of said decoding buffer,

providing an empty pointer associated with said decoding buffer, wherein said empty pointer points to one of the locations in said decoding buffer storing one of said digital samples to be transferred to said digital-to-analog converter for conversion,

incrementing said empty pointer to point to a next transfer one of the locations containing a next one of said digital samples to be transferred to said digital-to-analog converter, and

resetting said empty pointer to point to said first location in said decoding buffer in response to transferring one of said digital samples from said last location of said buffer to said digital-to-analog converter.

13. A method according to claim 12 further comprising, monitoring a distance between said fill pointer and said empty pointer, wherein said distance is measured in relation to a number of locations between a location pointed to by said fill pointer and a location pointed to by said empty pointer.

14. A method according to claim 13 further comprising, increasing said selected conversion rate in response to said distance becoming less than a predefined closeness threshold.

15. A method according to claim 13 further comprising, decreasing said selected conversion rate in response to said distance becoming greater than a predefined separation threshold.

16. A method according to claim 13 further comprising, increasing said frequency of said decoding master clock signal in response to said distance becoming less than a predefined closeness threshold.

17. A method according to claim 16 further comprising, increasing said selected conversion rate in dependence on said increasing of said frequency of said decoding master clock.

18. A method according to claim 13 further comprising, decreasing said frequency of said decoding master clock signal in response to said distance becoming greater than a predefined separation threshold.

19. A method according to claim 18 further comprising, decreasing said selected conversion rate in dependence on said decreasing of said frequency of said decoding master clock signal.

20. A method according to claim 12, wherein said generating of said decoding master clock signal further comprises,

frequency dividing a clock signal from said local oscillator to obtain a phase comparator reference signal,

determining an initial divide ratio for performing said frequency dividing based at least in part on said connect rate, and

phase locking said comparator reference signal to provide said decoding master clock signal at said substantially constant frequency.

21. A method according to claim 13, wherein generating a master clock signal further comprises,

frequency dividing a clock signal from said local oscillator to obtain a phase comparator reference signal,

determining an initial divide ratio for performing said frequency dividing based at least in part on said connect rate, and

phase locking said comparator reference signal to provide said decoding master clock signal at said substantially constant frequency.

22. A method according to claim 21 further comprising,

adjusting said frequency in dependence on said distance between said fill pointer and said empty pointer.

25. The method of claim 12 further comprising adjusting said frequency of said master clock to maintain said defined time relationship.

26. The method of claim 12 further comprising adjusting said sampling rate of said digital-to-analog converter to maintain said defined time relationship.