Method of and apparatus for sealing an hermetic lid to a semiconductor die

• US 6,764,875 B2
• Filed: 05/24/2001
• Issued: 07/20/2004
• Est. Priority Date: 07/29/1998
• Status: Expired due to Term

• Current Assignee: Silicon Light Machines Corporation (SCREEN Holdings Co., Ltd.)
• Original Assignee: Silicon Light Machines Corporation (SCREEN Holdings Co., Ltd.)
• Inventors: Shook, James Gill
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): VOCKRODT, JEFF B
• Application Number:
  US09/866,266
• Publication Number:
  US 20010022382A1
• Time in Patent Office: 1,153 Days
• Field of Search: 438/106, 438/110, 438/113, 438/116, 438/121, 257/680, 257/729, 257/730
• US Class Current: 438/106
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/67126 Apparatus for sealing, encapsulating, glassing, decapsulating or the like processes H01L23/02, H01L23/28
• CPC Class Codes: H01L 2224/02335 Free-standing redistribution layers
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques. An angle between the lid and the semiconductor device can be controlled by adjusting relative widths of one or both the layers of solderable materials.

Claims

1. A method of forming an hermetic seal to a semiconductor device comprising the steps of:

a. forming an active semiconductor device on a semiconductor substrate;

b. forming a lid sealing region surrounding the active semiconductor device, the lid sealing region having passivation spacer layer formed thereon such that the passivation spacer layer surrounds but does not substantially cover the active semiconductor device;

c. forming means for electrically coupling to the active semiconductor device on the surface of the substrate and outside the lid sealing region;

d. forming a first layer of solderable material on the passivation spacer layer;

e. on an optically transparent lid, forming a second layer of solderable material in a pattern conforming to the first layer of solderable material;

f. aligning the first layer of solderable material to the second layer of solderable material while providing a layer of solder therebetween; and

g. applying heat to melt the solder and seal the lid to the lid sealing region,

wherein the passivation spacer layer is configured to position the lid a finite distance from the active semiconductor device.

2. A method of forming an hermetic seal between a lid and a semiconductor device, wherein the lid and the semiconductor device are not parallel to one another comprising the steps of:

a. providing an active semiconductor device on a semiconductor substrate;

b. forming a substantially planarized lid sealing region surrounding the active semiconductor device;

c. forming means for electrically coupling to the active semiconductor device on the surface of the substrate and outside the lid sealing region;

d. forming a first layer of solderable material on the lid sealing region;

e. on an optically transparent lid, forming a second layer of solderable material in a pattern conforming to the first layer of solderable material;

f. aligning the first layer of solderable material to the second layer of solderable material while providing a layer of solder therebetween; and

g. applying heat to melt the solder and seal the lid to the lid sealing region,

wherein at least one of the first layer of solderable material and the second layer of solderable material has a substantially non-uniform cross section.

3. A method of forming hermetic seal between a lid and a semiconductor device, wherein the lid and the semiconductor device are not parallel to one another comprising the steps of:

a. providing an active semiconductor device on a semiconductor substrate;

b. forming a substantially planarized lid sealing region surrounding the active semiconductor device;

c. forming means for electrically coupling to the active semiconductor device on the surface of the substrate and outside the lid sealing region;

d. forming a first layer of solderable material on the lid sealing region;

e. on an optically transparent lid, forming a second layer of solderable material in a pattern conforming to the first layer of solderable material;

f. aligning the first layer of solderable material to the second layer of solderable material while providing a layer of solder therebetween; and

g. applying heat to melt the solder and seal the lid to the lid sealing region,

wherein at least one of the first layer of solderable material and the second layer of solderable material has a substantially non-uniform cross section around their respective lengths.

4. The method according to claim 3 wherein the lid sealing region and the first layer of solderable material have a substantially rectangular configuration having four legs joined at substantially right angles and one of the legs of the first layer of solderable material has a substantially dissimilar cross sectional area from the other three legs.

5. A method of concurrently forming an hermetic seal to each of a plurality of active semiconductor devices each comprising a plurality of ribbons all formed on a single semiconductor substrate comprising the steps of:

a. providing the plurality of active semiconductor devices on the semiconductor substrate;

b. forming a lid sealing region surrounding each of the active semiconductor devices, the lid sealing region having a passivation layer formed thereon such that the passivation spacer aver surrounds but does not substantially cover each of the active semiconductor devices;

c. forming means for electrically coupling to each of the active semiconductor devices on the surface of the substrate and outside the lid sealing region for each of the active semiconductor devices;

d. forming a first layer of solderable material on each of the passivation spacer layers;

e. on an optically transparent wafer, forming a second layer of solderable material in a pattern conforming to the first layer of solderable material;

f. aligning the first layer of solderable material to the second layer of solderable material while providing a layer of solder therebetween; and

g. applying heat to melt the solder and seal the wafer to the lid sealing regions,

wherein the passivation spacer layer is configured to position the lid a finite distance from the active semiconductor device.

6. A method of forming an hermetic seal between a transparent wafer and a semiconductor wafer having a plurality of semiconductor devices comprising the steps of:

a. providing a wafer having a plurality of active semiconductor devices ribbons on a semiconductor substrate;

b. forming a substantially planarized lid sealing region surrounding each one of the active semiconductor devices;

c. forming means for electrically coupling to each one of the active semiconductor devices on the surface of the substrate and outside each one of the lid sealing regions;

d. forming a first layer of solderable material on each one of the lid sealing regions;

e. on an optically transparent wafer, forming a second layer of solderable material in a pattern conforming to the first layer of solderable material;

f. aligning the first layer of solderable material to the second layer of solderable material while providing a layer of solder therebetween; and

g. applying heat to melt the solder and seal the optically transparent wafer to the lid sealing regions,

wherein at least one of the first layer of solderable material and the second layer of solderable material has a substantially non-uniform cross section around their respective lengths.

7. A method of forming an hermetic seal between a plurality of lids from an optically transparent wafer and a wafer of semiconductor devices, wherein at least one of the lids and its respective semiconductor device are not parallel to one another, the method comprising the steps of:

a. providing a plurality of active semiconductor devices on a semiconductor substrate;

b. forming a substantially planarized lid sealing region surrounding each one of the active semiconductor devices;

c. forming means for electrically coupling to each one of the active semiconductor devices on the surface of the substrate and outside each respective one of the lid sealing regions;

d. concurrently forming a first layer of solderable material on the lid sealing regions;

e. on an optically transparent wafer, forming a second layer of solderable material in a pattern conforming to the first layer of solderable material;

f. aligning the first layer of solderable material to the second layer of solderable material while providing a layer of solder therebetween; and

g. applying heat to melt the solder and seal the wafer to the lid sealing regions,

wherein at least one of the first layer of solderable material and the second layer of solderable material has a substantially non-uniform cross section around their respective lengths;

h. concurrently separating the semiconductor devices from the lids to form units; and

i. re-heating the units to provide a non-parallel relationship between the lids and their respective semiconductor devices.

8. The method according to claim 7 wherein the lid sealing region and the first layer of solderable material have a substantially rectangular configuration having four legs joined at substantially right angles and one of the legs of the first layer of solderable material has a substantially dissimilar cross sectional area from the other three legs.

9. A method of forming an hermetic seal to a semiconductor device comprising the steps of:

a. providing an active semiconductor device on a semiconductor substrate;

b. forming a lid sealing region on the semiconductor device and surrounding the active semiconductor device, the lid sealing region having a passivation spacer layer formed thereon;

c. forming means for electrically coupling to the active semiconductor device on the surface of the substrate and outside the lid sealing region;

d. forming a layer of polymeric epoxy on the passivation spacer layer;

e. providing a substantially flat optically transparent lid sized to conform to the lid sealing region;

f. aligning the lid to the layer of polymeric epoxy; and

g. applying heat to melt the polymeric epoxy and seal the lid to the lid sealing region.

10. The method according to claim 9 further comprising a spacing layer formed between the layer of polymeric epoxy and the display device.

11. The method according to claim 9 further comprising a spacing layer formed between the layer of polymeric epoxy and the lid.

12. A method of forming an hermetic seal to a semiconductor device comprising the steps of:

a. providing an active semiconductor device on a semiconductor substrate;

b. forming a lid sealing region surrounding the active semiconductor device, the lid sealing region having a passivation spacer layer formed thereon;

c. forming means for electrically coupling to the active semiconductor device on the surface of the substrate and outside the lid sealing region;

d. forming a layer of glass frit on the passivation spacer layer;

e. providing a substantially flat optically transparent lid sized to conform to the lid sealing region;

f. aligning the lid to the layer of glass frit; and

g. applying heat to melt the glass frit and seal the lid to the lid sealing region,

wherein the passivation spacer layer is configured to position the lid a finite distance from the active semiconductor device.

13. The method according to claim 12 further comprising a spacing layer formed between the layer of glass frit and the display device.

14. The method according to claim 12 further comprising a spacing layer formed between the layer of glass frit and the lid.