System and method for sensing memory cells of an array of memory cells
First Claim
1. A memory cell array sensing system comprising:
- an array of memory cells located on a first plane of an integrated circuit, the array of memory cells comprising groups of memory cells, wherein each group corresponds to a range of rows of the memory cells;
a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group, wherein no memory cells are located on the sense plane;
wherein multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells.
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Abstract
The invention includes a memory cell array sensing system. The memory cell array sensing system includes an array of memory cells located on a first plane of an integrated circuit. The array of memory cells includes groups of memory cells, wherein each group corresponds to a range of rows of the memory cells. A plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group. Multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells. A method of the invention includes electrically connecting multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells, and to sense amplifiers not belonging to the groups associated with the multiple memory cells; and sensing logic states of the multiple memory cells.
7 Citations
21 Claims
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1. A memory cell array sensing system comprising:
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an array of memory cells located on a first plane of an integrated circuit, the array of memory cells comprising groups of memory cells, wherein each group corresponds to a range of rows of the memory cells;
a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group, wherein no memory cells are located on the sense plane;
wherein multiple memory cells are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of sensing a state of a selected memory cells within a memory cell array sensing system, the memory cell array sensing system comprising an array of memory cells located on a first plane of an integrated circuit, the array of memory cells comprising groups of memory cells, wherein each group corresponds to a range of rows of the memory cells, the memory cell array sensing system further comprising a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group, wherein no memory cells are located on the sense plane, the method comprising:
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electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells; and
sensing logic states of the multiple memory cells. - View Dependent Claims (15)
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16. An MRAM memory comprising:
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an array of MRAM cells comprising rows and columns of MRAM cells located on a first plane of an integrated circuit, the array of MRAM cells comprising groups of MRAM cells, wherein each group corresponds to a range of rows of the MRAM cells;
a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group, wherein no MRAM cells are located on the sense plane;
wherein multiple MRAM are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cells. - View Dependent Claims (17, 18)
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19. A computer system comprising:
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a central processing unit;
MRAM memory connected to the central processing unit, the MRAM memory comprising;
an array of MRAM cells comprising rows and columns of MRAM cells located on a first plane of an integrated circuit, the array of MRAM cells comprising groups of MRAM cells, wherein each group corresponds to a range of rows of the MRAM cells;
a plurality of sense amplifiers located on a sense plane that is adjacent to the first plane, at least one sense amplifier being associated with each group, wherein no memory cells are located on the sense plane;
wherein multiple MRAM are simultaneously sensed by electrically connecting the multiple memory cells to sense amplifiers belonging to groups associated with the multiple memory cell. - View Dependent Claims (20, 21)
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Specification