Packet networks

• US 6,765,904 B1
• Filed: 12/14/1999
• Issued: 07/20/2004
• Est. Priority Date: 08/10/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Viswanathan, Vishu R., McCree, Alan V., Anandakumar, Krishnasamy
• Primary Examiner(s): VANDERPUYE, KENNETH N
• Application Number:
  US09/461,159
• Time in Patent Office: 1,680 Days
• Field of Search: 370/352, 370/353, 370/354, 370/355, 370/356, 370/395.1, 370/389, 370/400, 370/473
• US Class Current: 370/389
• CPC Class Codes: H04B 7/06 at the transmitting station
• CPC Class Codes: H04B 7/0671 using different delays between antennas
• CPC Class Codes: H04L 1/0007 by modifying the frame length
• CPC Class Codes: H04L 1/0018 based on latency requirement
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/11 Identifying congestion
• CPC Class Codes: H04L 47/2416 Real-time traffic
• CPC Class Codes: H04L 47/283 in response to processing delays, e.g. caused by jitter or round trip time [RTT]
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 65/752 adapting media to network capabilities
• CPC Class Codes: H04L 65/762 at the source reformatting of additional data in video distribution servers H04N21/2355
• CPC Class Codes: H04L 65/80 Responding to QoS
• CPC Class Codes: H04W 28/22 Negotiating communication rate
• CPC Class Codes: H04W 28/24 Negotiating SLA [Service Level Agreement]; Negotiating QoS [Quality of Service]
• CPC Class Codes: H04W 84/00 Network topologies

Abstract

A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22). Increasing the diversity rate (d11 to d22) while either reducing or keeping unchanged the overall transmission rate (sij+dij) is an important new improvement in even solely-time-diversity embodiments. In another form of the invention a single-chip integrated circuit includes a processor circuit (1511), and a rate-and-diversity control (1561). Here again, the diversity is contemplated to be time diversity, path diversity, and combined time/path diversity in various embodiments. Other embodiments disclosed encompass other processes, improved packets and packet ensembles, integrated circuits, chipsets, computer add-in cards, information storage articles, systems, computers, gateways, routers, cellular telephone handsets, wireless base stations, appliances, and packet networks, and other forms as claimed.

Claims

1. A packet network comprising:

A. a first computer and a second computer both adapted for media over packet transmission and reception, and

B. a packet network of routers and transmission media coupling said first computer and said second computer, said packet network including processor instruction bits supporting operations therein of reconstruction of a received packet stream with each packet having a primary stage and a secondary stage, the secondary stage having LPC parameters, and at least one of LTP lags, parity check, and adaptive and fixed codebook gains, the received packet stream having an instance of single packet loss, and the reconstruction comprising;

i. receiving a packet sequence represented by

2. The packet network of claim 1 in which the processor instruction bits define the performing an excitation to produce the following reconstructed packet sequence:

3. The packet network of claim 1 in which the secondary stage includes no fixed codebook pulses, and the processor instruction bits further define performing an excitation with an adaptive codebook contribution reconstructed from the adaptive codebook gain and LTP lag.

4. The packet network of claim 1 in which the secondary stage includes no fixed codebook pulses, and the processor instruction bits further define performing an excitation with an adaptive codebook contribution set to zero if the absolute value of the adaptive codebook gain is less than 0.4.

5. The packet network of claim 1 in which the secondary stage includes fixed codebook pulses, and the processor instruction bits further define performing an excitation with the fixed codebook pulses.

6. The packet network of claim 1 in which the secondary stage includes some of all the possible fixed codebook pulses, and the processor instruction bits further define performing the excitation with the some of all the possible fixed codebook pulses.

7. The packet network claim 1 in which the processor instruction bits further define performing an excitation with the fixed codebook pulses, other than the some of all the possible fixed codebook pulses, set to zero.