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CMOS imager with a self-aligned buried contact

  • US 6,767,811 B2
  • Filed: 10/24/2002
  • Issued: 07/27/2004
  • Est. Priority Date: 06/18/1999
  • Status: Expired due to Term
First Claim
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1. A method of forming a self-aligned buried contact in a CMOS imager, comprising the steps of:

  • providing a substrate comprising at least one transistor and at least one isolation region, said substrate including a p-type well having only an n-doped region, said n-doped region formed in the p-type well by ion implantation;

    forming a protective layer over said substrate;

    selectively removing at least a portion of said protective layer between a gate of said at least one transistor and another substrate feature selected from the group consisting of another transistor gate and said isolation region, to form a self-aligned plug opening; and

    forming a continuously conductive layer in said self-aligned plug opening to form a self-aligned buried contact.

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