Method of forming a silicon nitride-silicon dioxide gate stack

• US 6,767,847 B1
• Filed: 07/02/2002
• Issued: 07/27/2004
• Est. Priority Date: 07/02/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hu, Chien-Ming, Liang, Mong-Song, Chen, Shih-Chang, Chen, Chien-Hao, Yu, Mo-Chiun
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Maldonado, Julio J.
• Application Number:
  US10/187,704
• Time in Patent Office: 756 Days
• Field of Search: 438/216, 438/217, 438/261, 438/287, 438/289, 438/308, 438/762, 438/763, 438/766, 438/771, 438/772
• US Class Current: 438/771
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/2686 using incoherent radiation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method of forming a silicon nitride-silicon dioxide composite insulator layer for use as a gate insulator stack for an MOSFET device, has been developed. The method features formation of the silicon dioxide component of the gate insulator stack, after formation of the overlying silicon nitride component, allowing the gate insulator stack to be comprised with a nitrogen profile presenting enhanced barrier characteristic and less interface charge than counterpart silicon nitride-silicon dioxide composites formed wherein the silicon nitride component was deposited on an already grown underlying silicon dioxide layer. Oxygen ions, or oxygen radicals obtained via ultra-violet procedures, penetrate the silicon nitride component and locate in a top portion of the semiconductor substrate. Subsequent annealing allows reaction of the oxygen ions or radicals with a top portion of the semiconductor substrate resulting in the desired silicon dioxide component underlying silicon nitride.

Claims

1. A method of forming a gate insulator stack on a semiconductor substrate, comprising the steps of:

forming a first insulator layer on said semiconductor substrate;

placing energized oxygen radical in a top portion of said semiconductor substrate, with oxygen radicals obtained via ultra-violet procedures performed in an oxygen ambient, at an energy between about 0.1 to 1000 watts/cm², at a wavelength between about 100 to 300 nm; and

performing an anneal procedure to form a second insulator layer via reaction of said energized species and said semiconductor substrate, resulting in said gate insulator stack comprised of said first insulator layer overlying said second insulator layer.

2. The method of claim 1, wherein said first insulator layer is a silicon nitride layer at a thickness between about 10 to 20 Angstroms.

3. The method of claim 1, wherein said first insulator layer is a silicon nitride layer obtained via LPCVD or PECVD procedures.

4. The method of claim 1, wherein said first insulator layer is a silicon nitride layer obtained via plasma nitridization, performed at a power between about 100 to 1000 watts, at a pressure between about 0.1 to 10 torr, in an ammonia ambient.

5. The method of claim 1, further comprising an optional anneal procedure performed to said first insulator layer, at a temperature between about 900 to 1200°

C., for a tome between about 0.1 to 3 min, in an ambient comprised of nitrogen, N₂O, NO, argon and oxygen.

6. The method of claim 1, wherein said anneal procedure is performed at a temperature between about 900 to 1200°

C., for a time between about 0.1 to 3 min, in an ambient comprised with nitrogen, N₂O, NO, argon and oxygen.

7. The method of claim 1, wherein said second insulator layer is a silicon dioxide layer formed at a thickness between about 5 to 10 Angstroms.

8. A method of forming a silicon nitride-silicon dioxide gate insulator stack on a semiconductor substrate, comprising the steps of:

forming a silicon nitride layer on said semiconductor substrate;

performing a first anneal procedure;

performing an ultra-violet procedure to form oxygen radicals, and place said oxygen radicals in a top portion of said semiconductor substrate; and

performing a second anneal procedure to form a silicon dioxide layer via reaction of said oxygen radicals and said semiconductor substrate, resulting in said silicon nitride-silicon dioxide gate insulator stack.

9. The method of claim 8, wherein said silicon nitride layer is obtained via LPCVD or PECVD procedures.

10. The method of claim 8, wherein said silicon nitride layer is obtained via plasma nitridization, performed at a power between about 100 to 1000 watts, at a pressure between about 0.1 to 10 torr, in an ammonia ambient.

11. The method of claim 8, wherein said silicon nitride layer is obtained at a thickness between about 10 to 20 Angstroms.

12. The method of claim 8, wherein said first anneal procedure is performed at a temperature between about 900 to 1200°

C., for a time between about 0.1 to 3 min, in an ambient comprised of nitrogen, N₂O, NO, argon and oxygen.

13. The method of claim 8, wherein said ultra-violet procedure is performed in an oxygen ambient, at an energy between about 0.1 to 1000 watts/cm², at a wavelength between about 100 to 300 nm.

14. The method of claim 8, wherein said second anneal procedure is performed at a temperature between about 900 to 1200°

C., for a time between about 0.1 to 3 min, in an ambient comprised with nitrogen, N₂O, NO, argon and oxygen.

15. The method of claim 8, wherein said silicon dioxide layer is obtained at a thickness between about 5 to 10 Angstroms.