Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism

• US 6,779,049 B2
• Filed: 12/14/2000
• Issued: 08/17/2004
• Est. Priority Date: 12/14/2000
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation, Sony Interactive Entertainment Inc. (Sony Group Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wellman, John-David, Yamazaki, Takeshi, Gschwind, Michael, Suzuoki, Masakazu, Sathaye, Sumedh Wasudeo, Capek, Peter G., Hofstee, Harm Peter, Nair, Ravi, Kahle, James Allan, Altman, Erik R.
• Primary Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US09/736,585
• Publication Number:
  US 20020078308A1
• Time in Patent Office: 1,342 Days
• Field of Search: 710/22, 710/26, 710/27, 710/62, 710/74, 711/1, 711/5, 711/6, 711/147, 711/150, 711/153, 711/173, 711/202, 711/203, 711/205, 711/206, 711/207, 711/208, 711/209, 712/1, 712/14, 712/20, 712/27
• US Class Current: 710/22
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Claims

1. A system comprising:

a shared memory; and

a plurality of processing elements coupled to said shared memory, wherein at least one of said plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units, wherein said direct memory access controller comprises an address translation mechanism, wherein said plurality of attached processing units are configured to access said shared memory using said direct memory access controller.

2. The system as recited in claim 1, wherein said plurality of attached processing units is configured to issue a request to an associated direct memory access controller to access said shared memory, wherein said request specifies a range of addresses to be accessed as virtual addresses.

3. The system as recited in claim 2, wherein said associated direct memory access controller is configured to translate said range of virtual addresses to be accessed.

4. The system as recited in claim 3, wherein said associated direct memory access controller translates said range of virtual addresses to be accessed by retrieving an associated range of physical addresses from said address translation mechanism.

5. The system as recited in claim 4, wherein said associated direct memory access controller comprises a manager, wherein said manager is configured to search said address translation mechanism for said associated range of physical addresses.

6. The system as recited in claim 3, wherein said associated direct memory access controller translates said range of virtual addresses to be accessed by retrieving an associated range of physical addresses from a page table in said shared memory.

7. The system as recited in claim 6, wherein said associated direct memory access controller comprises a manager, wherein said manager is configured to search said page table in said shared memory for said associated range of physical addresses.

8. The system as recited in claim 3, wherein said range of virtual addresses to be accessed are translated into an associated range of physical addresses, wherein said associated range of physical addresses are pinned.

9. The system as recited in claim 1, wherein said address translation mechanism comprises a translation lookaside buffer.

10. A method for attached processing units accessing a shared memory in a system comprising the steps of:

issuing a request to an associated direct memory access controller to access said shared memory, by an attached processing unit element that does not contain an address translation mechanism, wherein said request specifies a range of addresses to be accessed as virtual addresses; and

translating said range of virtual addresses to be accessed to an associated range of physical addresses by said associated direct memory access controller.

11. The method as recited in claim 10, wherein said associated direct memory access controller translates said range of virtual addresses to be accessed by retrieving said associated range of physical addresses from an address translation mechanism.

12. The method as recited in claim 11, wherein said address translation mechanism is a translation lookaside buffer.

13. The method as recited in claim 10, wherein said associated direct memory access controller translates said range of virtual addresses to be accessed by retrieving said associated range of physical addresses from a page table in said shared memory.

14. The method as recited in claim 10, wherein said associated range of physical addresses are pinned.