Circuit for testing an integrated circuit

• US 6,781,398 B2
• Filed: 07/30/2002
• Issued: 08/24/2004
• Est. Priority Date: 07/31/2001
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Infineon Technologies AG
• Inventors: Berger, Hartmut, Adler, Frank
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Nguyen, Tung X.
• Application Number:
  US10/208,252
• Publication Number:
  US 20030035400A1
• Time in Patent Office: 756 Days
• Field of Search: 324/765, 324/158.1, 324/73.1, 324/763, 324/768, 324/769
• US Class Current: 324/762.02
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal input for receiving a reference signal. A comparator is in communication with the test signal input and with the reference signal input. The comparator is configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error. The error signal, if present, is stored in an error memory, in communication with the comparator output.

Claims

1. A test circuit br testing an integrated circuit, the test circuit comprising:

a test signal input for receiving a test signal from the integrated circuit;

a first reference signal input for receiving a first reference signal;

a first comparator in communication with the test signal input and with the first reference signal input, the first comparator configured to output a first error signal only when a test signal voltage of the test signal exceeds a reference signal voltage of the first reference signal;

a second reference signal input for receiving a second reference signal, and

a second comparator in communication with the test signal input and with the second reference signal input, the second comparator being configured to provide, at a second comparator output, a second error signal only when a reference signal voltage of the second reference signal exceeds the test signal voltage;

a first error memory, in communication with the first comparator output, for storing the first error signal; and

an error signal output in communication with the first error memory.

2. The test circuit of claim 1, wherein the first comparator is configured to output a binary error signal in response to a comparison of voltages of the test signal and the first reference signal.

3. The test circuit of claim 1, wherein the first error memory comprises a flip-flop.

4. The test circuit of claim 1, further comprising a reset signal input connected to the error first memory for erasing an error state thereof.

5. The test circuit of claim 1, further comprising a second error memory in communication with the second comparator output for storing the second error signal, the second error memory being in communication with the error signal output.

6. The test circuit of claim 5, wherein the first error memory and the second error memory are configured to be read separately from each other at the error signal output.

7. A system for testing an integrated circuit, the system comprising:

a test circuit including;

a test signal input for receiving a test signal from the integrated circuit;

a first reference signal input for receiving a first reference signal;

a first comparator in communication with the test signal input and with the first reference signal input, the first comparator configured to output a first error signal only when a test signal voltage of the test signal exceeds a reference signal voltage of the first reference signal;

a second reference signal input for receiving a second reference signal, and

a second comparator in communication with the test signal input and with the second reference signal input, the second comparator being configured to provide, at a second comparator output, a second error signal only when a reference signal voltage of the second reference signal exceeds the test signal voltage;

a first error memory, in communication with the first comparator output, for storing the first error signal; and

an error signal output in communication with the first error memory;

a programmable driver output for outputting the first reference signal to the first reference signal input of the test circuit, and

a test result input in communication with the error signal output for receiving the first error signal.

8. The system of claim 7, wherein the test circuit comprises an ASIC (“

application specific integrated circuit”

).

9. The system of claim 7, wherein the test circuit comprises a programmable logic array.

10. The system of claim 7, wherein the programmable driver output comprises an analog high-speed output.

11. The system of claim 10, wherein the test result input is a low speed input.

12. The system of claim 7, further comprising a second programmable driver output in communication with the test signal input.

13. The system of claim 12, wherein the second programmable driver output forms an active termination of the test signal input.

14. A system for testing an integrated circuit, the system comprising:

a test circuit including;

a test signal input for receiving a test signal from the integrated circuit;

a first reference signal input for receiving a first reference signal;

a first comparator in communication with the test signal input and with the first reference signal input, the first comparator configured to output a first error signal only when a test signal voltage of the test signal exceeds a reference signal voltage of the first reference signal;

a second reference signal input for receiving a second reference signal, and

a second comparator in communication with the test signal input and with the second reference signal input, the second comparator being configured to provide, at a second comparator output, a second error signal only when a reference signal voltage of the second reference signal exceeds the test signal voltage;

a first error memory, in communication with the first comparator output, for storing the first error signal; and

an error signal output in communication with the first error memory;

a first programmable driver output for outputting the first reference signal to the first reference signal input of the test circuit,

a second programmable driver output for outputting the second reference signal to the second reference signal input, and

a test result input in communication with the error signal output for receiving the error signal.

15. A method of testing a test signal of a DDR-DIMM, the method comprising:

providing a system, and

providing the test signal to the system, the system including;

a test signal input for receiving a test signal from the integrated circuit;

a first reference signal input for receiving a first reference signal;

a first comparator in communication with the test signal input and with the first reference signal input, the first comparator configured to output a first error signal only when a test signal voltage of the test signal exceeds a reference signal voltage of the first reference signal;

a second reference signal input for receiving a second reference signal, and

a second comparator in communication with the test signal input and with the second reference signal input, the second comparator being configured to provide, at a second comparator output, a second error signal only when a reference signal voltage of the second reference signal exceeds the test signal voltage;

a first error memory, in communication with the first comparator output, for storing the first error signal; and

an error signal output in communication with the first error memory;

a programmable driver output for outputting the first reference signal to the first reference signal input of the test circuit, and

a test result input in communication with the first error signal output for receiving the first error signal.

16. A method of testing a test signal generated by an integrated circuit, the method comprising:

providing the test signal to a test signal input of a test circuit;

providing a reference signal into a reference signal input of the test circuit;

comparing the test signal and the reference signal with a comparator;

storing an error signal into an error memory only when a test signal voltage of the test signal exceeds a reference signal voltage of the reference signal; and

reading the error signal from the error memory.

17. The method of claim 16, wherein comparing the test signal comprises providing an external control signal to the comparator for causing the comparator to enter a comparison mode.