Symmetric stack up structure for organic BGA chip carriers

• US 6,784,536 B1
• Filed: 08/23/2001
• Issued: 08/31/2004
• Est. Priority Date: 12/08/2000
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Eslamy, Mohammad
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/938,075
• Time in Patent Office: 1,104 Days
• Field of Search: 257/706, 257/729, 257/738, 257/762, 257/796, 257/678, 257/712, 257/792, 257/720, 257/747, 257/717, 257/675
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 Multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

An improved structure for an organic ball-grid array chip carrier having an organic substrate attached to a metal heat sink plate to prevent the chip carrier from warping. A supplemental organic substrate is attached to the metal heat sink plate on the side opposite from the functional organic substrate to provide symmetry to the bending forces resulting from the mismatch in coefficients of thermal expansion between the organic substrate and the metal heat sink plate.

Claims

1. A semiconductor chip carrier comprising:

a primary substrate;

a metal heat sink plate, whose thermal coefficient of expansion is substantially different from that of said primary substrate, having a first side and an opposing second side where said primary substrate is attached to said first side;

a supplemental substrate being attached to said second side of said metal heat sink plate, wherein said metal heat sink plate is between said primary substrate and said supplemental substrate; and

said supplemental substrate is constructed from a material having a substantially similar coefficient of thermal expansion as that of said primary substrate so that the presence of the supplemental substrate prevents the semiconductor chip carrier from warping.

2. A semiconductor chip carrier according to claim 1, wherein said supplemental substrate is constructed from a same material as said primary substrate.

3. A semiconductor chip carrier according to claim 1, wherein said primary substrate is constructed from a material selected from one of Bis-malesimide triazine epoxy, FR4, polyimide, and polytetrafluoroethylene.

4. A semiconductor chip carrier according to claim 1, wherein said chip carrier is a ball-grid array chip carrier.

5. A semiconductor chip carrier according to claim 1, wherein said metal heat sink plate consists of a metal selected from one of Cu, Cu—

W, Al, and alloys thereof.

6. A semiconductor chip carrier according to claim 1, wherein said supplemental substrate has a Cu—

Ni finish layer.

7. A semiconductor chip carrier according to claim 1, wherein said supplemental substrate has a cavity exposing a portion of said metal heat sink plate.

8. A semiconductor chip carrier according to claim 1, wherein said primary substrate comprises a hole forming a die-attach cavity wherein the semiconductor chip is attached to the first side of the metal heat sink plate within the die-attach cavity.