Solid-state imaging device and method for controlling same

• US 6,784,933 B1
• Filed: 08/31/2000
• Issued: 08/31/2004
• Est. Priority Date: 09/10/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakai, Hiroto
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Ye, Lin
• Application Number:
  US09/653,190
• Time in Patent Office: 1,461 Days
• Field of Search: 348/303, 348/307, 348/308, 348/311, 348/313, 348/294, 348/302, 257/290, 257/234, 257/291, 257/292, 438/57, 438/73, 365/104
• US Class Current: 348/302
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A pixel unit 1 comprises a nonvolatile memory transistor MT, which is formed on a p-type well 12 of a semiconductor substrate 10 and which has a floating gate 14 and a control gate 16, and selecting gate transistors ST1 and ST2 which share a diffusion layer 17 with the memory transistor MT and which is formed on both sides of the memory transistor MT. The memory transistor MT has a photoelectric converting region PD in the substrate directly below the floating gate 14. By irradiating the memory transistor MT with light while a positive writing voltage is applied to the control gate 16, charges generated in the photoelectric converting region PD are injected into the floating gate 14 to be held therein, so that pixel information is stored as a threshold voltage. Thus, it is possible to provide a solid-state imaging device with memory function, which has a small unit pixel area, a small electric current consumption and a simple structure and which can be produced without the need of any complicated producing processes.

Claims

1. A solid-state imaging device comprising:

a semiconductor substrate;

a nonvolatile memory transistor which is formed on the semiconductor substrate and which has a charge storage layer and a control gate, a photoelectric converting region being arranged below the charge storage layers and in the semiconductor substrate, the nonvolatile memory transistor being irradiated with light to generate charges in the photoelectric converting region and to inject the charges into the charge storage layer, the charges being stored in the charge storage layer as pixel information; and

at least two selecting gate transistors, each of which is formed on both sides of the nonvolatile memory transistor so as to share a diffusion layer with the nonvolatile memory transistor.

2. A solid-state imaging device as set forth in claim 1, which has an image pickup mode, in which the charges generated in the photoelectric converting region are injected into the charge storage layer on the basis of the FN tunneling by turning off the selecting gate transistors and by irradiating the nonvolatile memory transistor with light while a writing voltage is applied to the control gate of the nonvolatile memory transistor, and

a reading mode, in which the pixel information is read out by turning on the selecting gate transistors and by applying a reading voltage to the control gate of the nonvolatile memory transistor to detect a conducting state of the nonvolatile memory transistor.

3. A solid-state imaging device as set forth in claim 1, wherein a plurality of pixel units are arranged on the semiconductor substrate in the form of a matrix so as to extend in row and column directions, each of the pixel units comprising the nonvolatile memory transistor and two the selecting gate transistors arranged on both sides thereof.

4. A solid-state imaging device as set forth in claim 3, which further comprises a shading film formed on the semiconductor substrate, the shading film having openings, each of which corresponds to a region of each of the nonvolatile memory transistors.

5. A solid-state imaging device as set forth in claim 3, which further comprises micro lenses, each of which condenses light on a region of each of the nonvolatile memory transistors from the top, the micro lenses being formed on the semiconductor substrate.

6. A solid-state imaging device as set forth in claim 3, which further comprises color filters corresponding to each of the pixel units, the color filters being formed on the semiconductor substrate.

7. A solid-state imaging device as set forth in claim 3, which further comprises:

a shading film formed on the semiconductor substrate, the shading film having openings, each of which corresponds to a region of each of the nonvolatile memory transistors;

color filters corresponding to each of the pixel units; and

micro lenses, each of which condenses light on a region of each of the nonvolatile memory transistors from the top through a corresponding one of the color filters.

8. A solid-state imaging device as set forth in claim 3, which further comprises:

driving lines, each of which is connected commonly to the control gate of the nonvolatile memory transistors of the pixel units which are arranged so as to extend in the row directions;

signal output lines, each of which is connected commonly to the diffusion layer of the selecting gate transistors, each of which is arranged on one side of the nonvolatile memory transistors of the pixel units which are arranged so as to extend in the column directions, each of the diffusion layers being opposite to each of the nonvolatile memory transistors; and

a common source line connected commonly to the diffusion layer of the selecting gate transistors, each of which is arranged on the other side of the nonvolatile memory transistors of the pixel units which are arranged so as to extend in the column directions, each of the diffusion layers being opposite to each of the nonvolatile memory transistors.

9. A solid-state imaging device as set forth in claim 8, which further comprises current amplification type sense amplifier circuits, each of which is connected to each of the signal output lines.

10. A solid-state imaging device as set forth in claim 9, which further comprises a shift register inputted outputs in parallel from the sense amplifier circuits, and converting them into serial data to output.

11. A solid-state imaging device as set forth in claim 8, which further comprises voltage amplification type sense amplifier circuits, each of which is connected to each of the signal output lines.

12. A solid-state imaging device as set forth in claim 11, which further comprises a shift register inputted outputs in parallel from the sense amplifier circuits, and converting them into serial data to output.

13. A solid-state imaging device as set forth in claim 8, which further comprises a sense amplifier circuit connected commonly to the signal output lines, the sense amplifier circuit being inputted outputs sequentially from the signal output lines to output serial data.

14. A method for controlling a solid-state imaging device comprising:

a semiconductor substrate;

a nonvolatile memory transistor which is formed on the semiconductor substrate and which has a charge storage layer and a control gate, a photoelectric converting region being arranged below the charge storage layers and in the semiconductor substrate, the nonvolatile memory transistor being irradiated with light to generate charges in the photoelectric converting region and to inject the charges into the charge storage layer, the charges being stored in the charge storage layer as pixel information; and

at least two selecting gate transistors, each of which is formed on both sides of the nonvolatile memory transistor so as to share a diffusion layer with the nonvolatile memory transistor,

wherein a plurality of pixel units are arranged on the semiconductor substrate in the form of a matrix so as to extend in row and column directions, each of the pixel units comprising the nonvolatile memory transistor and two the selecting gate transistors arranged on both sides thereof, the method comprising;

an erase step for electrically emitting charges from the charge storage layer of the nonvolatile memory transistors;

an image pickup step for turning off the selecting gate transistors and irradiating the nonvolatile memory transistors with light while a writing voltage is applied to the control gate of the nonvolatile memory transistors, to inject charges generated in the photoelectric converting region of a corresponding one of the nonvolatile memory transistors, into the charge storage layer of the corresponding one of the nonvolatile memory transistors; and

a reading step for reading the pixel information by applying a reading voltage to the control gate of a corresponding one of the nonvolatile memory transistors while the selecting gate transistors are turned on.

15. A method for controlling a solid-state imaging device comprising:

a semiconductor substrate;

a nonvolatile memory transistor which is formed on the semiconductor substrate and which has a charge storage layer and a control gate, a photoelectric converting region being arranged below the charge storage layers and in the semiconductor substrate, the nonvolatile memory transistor being irradiated with light to generate charges in the photoelectric converting region and to inject the charges into the charge storage layer, the charges being stored in the charge storage layer as pixel information; and

at least two selecting gate transistors, each of which is formed on both sides of the nonvolatile memory transistor so as to share a diffusion layer with the nonvolatile memory transistor,

wherein a plurality of pixel units are arranged on the semiconductor substrate in the form of a matrix so as to extend in row and column directions, each of the pixel units comprising the nonvolatile memory transistor and two the selecting gate transistors arranged on both sides thereof, the method comprising;

an erase step for electrically emitting charges from the charge storage layer of the nonvolatile memory transistors;

a pre-writing step for turning off the selecting gate transistors and applying a first writing voltage to the control gates of the nonvolatile memory transistors, to inject charges, which exist in an inversion layer formed in a channel region of a corresponding one of the nonvolatile memory transistors, into the charge storage layer of the corresponding one of the nonvolatile memory transistors, the charges being stored in each of the charge storage layers as dummy pixel information; and

a pre-reading step for reading and storing the dummy pixel information by applying a reading voltage to the control gate of each of the nonvolatile memory transistors while each of the selecting gate transistors are turned on;

a pre-charging step for pre-charging a channel region of each of the nonvolatile memory transistors on the basis of the dummy pixel information;

an image pickup step for turning off the selecting gate transistors and irradiating the nonvolatile memory transistors with light while a second writing voltage is applied to the control gate of the nonvolatile memory transistors, to inject charges generated in the photoelectric converting region of a corresponding one of the nonvolatile memory transistors, into the charge storage layer of the corresponding one of the nonvolatile memory transistors, the charges being stored in the charge storage layer as the pixel information; and

a reading step for reading the pixel information by applying a reading voltage to the control gate of a corresponding one of the nonvolatile memory transistors while each of the selecting gate transistors are turned on.