Dual ported memory for digital image sensor
First Claim
1. An image sensor, comprising:
- a sensor array generating digital signals representing a number of samples of an image of a scene, data memory having a first port and a second port, the first port coupled to the sensor array by a first data bus having a first bus width to communicate with the sensor array, the second port coupled to a processor array by a second data bus having a second bus width; and
wherein the data memory receives from the first data bus a first one of the samples of the image and is updated only at certain cells therein for subsequent ones of the samples; and
the samples in the data memory is accessed by the processor from the second data bus.
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Abstract
An image sensor architecture that accommodates the relative mismatch of bus width between the image sensor, processor, and memory is disclosed. The preferred embodiment of the invention provides a dual-ported memory structure having a relatively wide data port for receiving data from the image sensor and having a relatively narrow data port for communicating data to and from the processor. In one embodiment of the invention, the memory is organized into banks of a specific width. The banks may be accessed sequentially by the processor, such that the bus width is equivalent to the bank width, and the banks may be accessed simultaneously, such that the bus width is equivalent to the combined bank widths. A simple switching means, operating under processor control, reconfigures the memory on the fly.
88 Citations
18 Claims
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1. An image sensor, comprising:
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a sensor array generating digital signals representing a number of samples of an image of a scene, data memory having a first port and a second port, the first port coupled to the sensor array by a first data bus having a first bus width to communicate with the sensor array, the second port coupled to a processor array by a second data bus having a second bus width; and
wherein the data memory receives from the first data bus a first one of the samples of the image and is updated only at certain cells therein for subsequent ones of the samples; and
the samples in the data memory is accessed by the processor from the second data bus.- View Dependent Claims (2, 3, 4, 5, 6)
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7. An image sensor, comprising:
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a sensor array, fabricated in an integrated circuit, generating samples representing one or more images of a scene, the image sensor further comprising a first data bus having a first bus width;
a processor including a data bus having a second bus width having a second bus width that is not identical to the first bus width, wherein the controller is fabricated in the integrated circuit; and
a data memory, in communication with the sensor array and for storing values representative of the samples, including means for accommodating both the first and the second data bus widths, wherein the data memory is fabricated in the integrated circuit. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An image sensor, comprising:
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a sensor array generating samples representing one or more images of a scene, the image sensor further including a data bus having a first bus speed and/or operating voltage, wherein the sensor array is fabricated in an integrated circuit;
a controller for manipulation of values in a data memory, the controller further comprising a data bus having a second bus speed and/or operating voltage that is not the same of that of the sensor array bus speed and/or operating voltage, wherein the controller is fabricated in the integrated circuit; and
a data memory, in communication with the sensor array, for storing values representative of the signals, the data memory further comprising means for accommodating both the first and the second data bus speeds and/or operating voltages, wherein the data memory is fabricated in the integrated circuit.
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Specification