Low power phase locked loop frequency synthesizer

• US 6,795,517 B1
• Filed: 09/18/2000
• Issued: 09/21/2004
• Est. Priority Date: 09/25/1999
• Status: Expired due to Term

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Marshall, Paul R.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Perilla, Jason M.
• Application Number:
  US09/663,674
• Time in Patent Office: 1,464 Days
• Field of Search: 375/376, 375/374, 375/147, 327/147, 331/25, 331/14
• US Class Current: 375/376
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 2207/18 Temporarily disabling, deactivating or stopping the frequency counter or divider
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted

Abstract

A phase locked loop frequency (PLL) synthesizer in which the scaled output of a reference oscillator(24) is compared with the scaled output of a voltage controlled oscillator(VCO)(10) in a comparator(22) to provide an error voltage which is integrated to form a frequency control voltage for the VCO. When the VCO has stabilized, the PLL is interrupted by the opening of a switch(32) in the output circuit of the comparator(22) and de-energizing the reference oscillator(24), scalers(18,26) and the comparator(22). A capacitor(36) which has been charged by the frequency control voltage maintains the output frequency of the VCO. Periodically the de-energized stages are re-energized and the switch(32) is closed to restore the PLL thereby enabling the VCO(10) to stabilize again after which the cycle of operations is repeated. A technique is disclosed for avoiding a jump in the VCO frequency when the switch(32) is closed.

Claims

1. A phase locked loop (PLL) frequency synthesiser comprising a reference oscillator, a first frequency determining means coupled to an output of the reference oscillator, a voltage controlled oscillator (VCO) having a control input and an output, a second frequency determining means coupled to the output of the VCO, phase comparing means coupled to outputs of the first and second frequency determining means, integrating means coupling an output of the phase comparing means to the control input of the VCO, switching means in the circuit path from the phase comparing means to the integrating means, said switching means when conductive completing the PLL but when non-conductive interrupting the PLL, voltage storing means for applying a control voltage to the control input of the VCO when the PLL is interrupted, control means for providing control signals for switching-off the reference oscillator, the phase comparing means, and the first and second frequency determining means and for rendering the switching means non-conductive to interrupt the PLL, the VCO producing an output signal in accordance with the voltage provided by the voltage storage means, and control signals for switching-on the reference oscillator and the first and second frequency determining means, and for providing control signals for forcing a 90 degree phase shift between the first and second frequency determining means and for rendering the switching means conductive to restore the PLL.

2. A frequency synthesiser as claimed in claim 1, characterised in that the first and second frequency determining means comprise first and second frequency scaling means, respectively.

3. A frequency synthesiser as claimed in claim 1, characterised in that the first frequency determining means comprises frequency scaling means and in that the second frequency determining means comprises frequency measuring means.

4. A frequency synthesiser as claimed in claim 1, characterised in that the first frequency determining means comprises frequency measuring means and the second frequency determining means comprises frequency scaling means.

5. A frequency synthesiser as claimed in claim 1, characterised in the means for applying the control voltage comprises means for storing a representation of the voltage applied to the control input prior to the interruption of the PLL.

6. A transceiver comprising a receiving stage and a source of local oscillator signals coupled to the receiving stage, said source comprising a phase locked loop (PLL) frequency synthesiser comprising a reference oscillator, a first frequency determining means coupled to an output of the reference oscillator, a voltage controlled oscillator (VCO) having a control input and an output, a second frequency determining means coupled to the output of the VCO, phase comparing means coupled to outputs of the first and second frequency determining means, integrating means coupling an output of the phase comparing means to the control input of the VCO, switching means in the circuit path from the phase comparing means to the integrating means, said switching means when conductive completing the PLL but when non-conductive interrupting the PLL, voltage storage means for applying a control voltage to the control input of the VCO when the PLL is interrupted, control means for providing control signals for switching-off the reference oscillator, the phase comparing means, and the first and second determining means and for rendering the switching means non-conductive to interrupt the PLL, the VCO producing an output signal in accordance with the voltage provided by the voltage storage means, and control signals for switching-on the reference oscillator and the first and second frequency determining means, and for providing control signals for forcing a 90 degree phase shift between the first and second frequency determining means and for rendering the switching means conductive to restore the PLL.

7. A transceiver as claimed in claim 6, characterised in that the first and second frequency determining means comprise first and second frequency scaling means, respectively.

8. A wireless remote control device comprising a transceiver including a receiving stage and a source of local oscillator signals coupled to the receiving stage, said source comprising a phase locked loop (PLL) frequency synthesiser comprising a reference oscillator, a first frequency determining means coupled to an output of the reference oscillator, a voltage controlled oscillator (VCO) having a control input and an output, a second frequency determining means coupled to the output of the VCO, phase comparing means coupled to outputs of the first and second frequency determining means, integrating means coupling an output of the phase comparing means to the control input of the VCO, switching means in the circuit path from the phase comparing means to the integrating means, said switching means when conductive completing the PLL but when non-conductive interrupting the PLL, voltage storage means for applying a control voltage to the control input of the VCO when the PLL is interrupted, control means for providing control signals for switching-off the reference oscillator, the phase comparing means, and the first and second frequency determining means and for rendering the switching means non-conductive to interrupt the PLL, the VCO producing an output signal in accordance with the voltage provided by the voltage storage means, and control signals for switching-on the reference oscillator and the first and second frequency determining means, and for providing control signals for forcing a 90 degree phase shift between the first and second frequency determining means and for rendering the switching means conductive to restore the PLL.