Memory interface for reading/writing data from/to a memory

• US 6,799,246 B1
• Filed: 12/16/1997
• Issued: 09/28/2004
• Est. Priority Date: 06/24/1993
• Status: Expired due to Fees

• Current Assignee: Talon Research LLC
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Jones, Anthony Mark, Smith, Colin, Barnes, Mark, Barnes, David Andrew, Claydon, Anthony Peter J., Birch, Nicholas, Patterson, Donald W. Walker, Dewar, Kevin Douglas, Kuligowski, Andrew Peter, Finch, Helen Rosemary, Sotheran, Martin William, Robbins, William Philip, Wise, Adrian P.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US08/991,234
• Time in Patent Office: 2,478 Days
• Field of Search: 711/104, 711/105, 711/117, 711/217, 711/218, 711/219, 710/52, 710/39, 710/53
• US Class Current: 711/117
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer

Abstract

A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Claims

1. A memory interface for connecting a bus to memory, comprising:

an input for receiving a plurality of data words from said bus;

a swing buffer for buffering said data words received from said bus;

an address input for receiving from said bus addresses associated with said plurality of data words;

a generator for generating a series of addresses in said memory into which said buffered data words may be written, said series of addresses being derived from said received addresses; and

a writer for writing said buffered data words into said memory at said generated addresses.

2. The memory interface of claim 1 wherein said memory operates in page addressing mode, and said generator includes a row address generator for generating row addresses and a column address generator for generating column addresses based on said received address.

3. The memory interface of claim 2 wherein said memory is a DRAM, said bus includes a two wire interface, each of said input and buffer includes a two wire interface, and said plurality of data words and said received addresses are in the form of a token.

4. The memory interface of claim 1 further including a determiner for determining whether said input and said buffer have received and buffered said plurality of data words.

5. A memory interface for connecting a bus to a memory, comprising:

a plurality of data words stored in said memory at predetermined addresses;

an address input including a swing buffer for receiving from said bus one of said addresses associated with said plurality of data words;

a generator for generating a series of addresses for addressing said plurality of data words in said memory, said series of addresses being derived from said received addresses to buffer data words read from said memory;

a reader for reading from said memory said plurality of data words by use of said series of addresses generated by said generator; and

a writer for writing said data words into a buffer.

6. The memory interface of claim 5 wherein said memory operates in page addressing mode, and said generator includes a row address generator for generating row addresses, and a column address generator for generating column addresses based on said received address.

7. The memory interface of claim 6 wherein said memory is a DRAM, said received address is in the form of a token, and each of said bus and said address input includes a two-wire interface.

8. The memory interface of claim 5 further including means for determining whether said address input has received and buffered said plurality of data words.