High output high efficiency low voltage charge pump

• US 6,801,076 B1
• Filed: 04/28/2000
• Issued: 10/05/2004
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd A.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US09/560,121
• Time in Patent Office: 1,621 Days
• Field of Search: 327/536, 327/537, 327/259, 327/589, 363/59, 363/60, 307/110, 365/203
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

The charge pump circuit includes an oscillator to generate an oscillating signal. The charge pump circuit further includes a primary phase generator, which receives the oscillating signal and generates first and a second phase signals that are non-overlapping and crossing around their high points. The primary phase generates further generates third and fourth phase signals that non-overlapping and crossing around their low points. The charge pump circuit further includes a secondary phase generator, which receives the first and second phase signals from the primary phase generator and generates delayed fifth and sixth phase signals. The charge circuit further includes first and second pre-boot precharge capacitors, which receive the first and second phase signals. The charge circuit further includes first and second pre-boot capacitors, which receive the first and second phase signals, and is further precharged by the first and second pre-boot precharge capacitors respectively during a first phase and a second phase respectively to a first pre-determined level. The charge pump further includes first and second main pump precharge capacitors, which receive the first and second phase signals from the primary phase generator during the first and second phases respectively. The charge pump circuit further includes first and second main pump capacitors for outputting the charge. According to one embodiment, the charge pump is generally prebooting one of the main pump capacitors to a predetermined boot level, while it is outputting the charge from the other main pump capacitor. As a result, the pre-boot time is hidden during a charge out. This enables the charge pump to run at a faster cycle time which can result in a higher output. This can also enable the charge pump to produce more charge for a given size of a capacitor.

Claims

1. A charge pump, comprising:

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second preboot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

2. The charge pump of claim 1, further comprising:

first and second sharing transistors coupled to the first and second pre-boot pre-charge capacitors and the first and second pre-boot capacitors to provide a path that charge shares the first and second pre-boot capacitors to the first and second main pump capacitors.

3. A charge pump, comprising:

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second preboot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively,

wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during the first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the second predetermined level is moves to a third predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, and wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

4. A charge pump, comprising:

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors , wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the second predetermined level moves to a third predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, and wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

5. The charge pump of claim 4, wherein the plurality of phase generators comprises:

a primary phase generator; and

a secondary phase generator coupled to the primary phase generator, wherein the first and second preboot capacitors are coupled to the primary phase generator, and the first and second main pump capacitors are coupled to the secondary phase generator and the first and second preboot capacitors, respectively.

6. A charge pump, comprising:

an oscillator to generate a first and a second phase during a phase cycle;

a primary phase generator coupled to the oscillator;

a secondary phase generator coupled to the primary phase generator;

first and second preboot capacitors coupled to the primary phase generator, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the secondary phase generator, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to one of the primary and secondary phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively,

wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the primary phase generator during the first and second phases, respectively, wherein the second predetermined level moves to a third predetermined level in response to the secondary phase generator during the first and second phases, respectively, wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, and wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

7. The charge pump of claim 6, further including a power source, wherein the power source includes an output voltage approximately in the range of about 1 to 2.5 volts.

8. The charge pump of claim 6, wherein the primary phase generator comprises:

an inverter, coupled to the oscillator to receive an input signal from the oscillator based on the phase cycle and providing output signals which are 180 degrees out of phase; and

cross coupled gates coupled to the inverter to receive the output signals from the inverter and outputting signals that are non-overlapping and crossing around high points of their signals during the first and second phases, respectively, and further outputting signals that are non-overlapping and crossing around low points of their signals during the first and second phases, respectively.

9. The charge pump of claim 6, wherein the secondary phase generator comprises a delay circuit coupled to the primary phase generator, including an input receiving signals that are non-overlapping and crossing around high points of their signals from the primary phase generator, and providing an output signal having a predetermined delay from the input signal.

10. The charge pump of claim 9, wherein the predetermined delay is approximately in the range of about 10 to 30 nanoseconds.

11. The charge pump of claim 9, wherein the first and second preboot capacitors are coupled to the primary phase generator to receive input signals that are non-overlapping and crossing around high points and low points of their signals, and provide an output signal to preboot the first and second main capacitors to the first predetermined level during the first and second phases, respectively.

12. The charge pump of claim 11, wherein the first predetermined level is approximately in the range of about 1 to 5 volts.

13. The charge pump of claim 11, wherein the first main pump precharge capacitor includes an input for receiving a signal among the signals that are non-overlapping and crossing around high points of their signals and includes an output for providing an output signal to precharge the first main pump precharge capacitor to the second predetermined level.

14. The charge pump of claim 13, wherein the second predetermined level is approximately in the range of about 1 to 5 volts.

15. The charge pump of claim 13, wherein the first and second precharge capacitors further comprise sharing transistors to precharge the first and second precharge capacitors.

16. The charge pump of claim 15, wherein the first and second main pump capacitors coupled to the secondary phase generator, and the first and second precharge capacitors, respectively, including an input receiving the delayed signal from the secondary phase generator to move the second predetermined level to the third predetermined level, and dumping an output during the first and second phases, respectively.

17. The charge pump of claim 16, wherein the third predetermined level is approximately in the range of about 1 to 5 volts.

18. The charge pump of claim 16, wherein the first and second gating devices coupled to the first and second main pump capacitors include an input to receive the dumped signal from the first and second main pump capacitors and an output to receive a charge to an external load.

19. The charge pump of claim 16, wherein the outputted charge is approximately in range of about 1.5 to 5 volts.

20. A charge pump, comprising:

an oscillator to generate first and second phases during a phase cycle;

a primary phase generator coupled to the oscillator;

a secondary phase generator coupled to the primary phase generator;

first and second preboot capacitors coupled to the primary phase generator, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the secondary phase generator, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to one of the primary and secondary phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors are prebooted to a first predetermined level of approximately in the range of about 1 to 5 volts by the first and second preboot capacitors during the first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level of approximately in the range of about 1 to 5 volts in response to the primary phase generator during the first and second phases, respectively, wherein the second predetermined level is moved to a third predetermined level of approximately in the range of about 1 to 1.5 volts in response to the secondary phase generator during the first and second phases, respectively, wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, and wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

21. A charge pump, comprising:

an oscillator to generate a first and a second phase during a phase cycle;

a primary phase generator coupled to the oscillator further includes;

an inverter, coupled to the oscillator to receive an input signal from the oscillator based on the phase cycle and providing output signals which are 180 degrees out of phase; and

cross coupled gates coupled to the inverter to receive the output signals from the inverter and to output signals that are non-overlapping and crossing around high points of their signals during the first and second phases, respectively, and further to output signals that are non-overlapping and crossing around low points of their signals during the first and second phases, respectively;

a secondary phase generator coupled to the primary phase generator receives the signals that are non-overlapping and crossing around high points of their signals from the primary phase generator;

first and second preboot capacitors coupled to the primary phase generator receives the signals that non-overlapping and crossing around high points and low points of their signals from the primary phase generator, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the secondary phase generator, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to one of the primary and secondary phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second preboot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during the first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the primary phase generator during the first and second phases, respectively, wherein the second predetermined level is moved to a third predetermined level in response to the secondary phase generator during the first and second phases, respectively, wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, and wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

22. A charge pump, comprising:

an oscillator to generate a first phase and a second phase during a phase cycle;

first and second primary phase generators coupled to the oscillator,

first and second secondary phase generators coupled to the first and second primary phase generators, respectively;

first and second preboot capacitors coupled to the first and second primary phase generators, respectively, wherein each of the first and second preboot capacitors has an output;

a first main pump capacitor coupled to the first secondary phase generator and the first preboot capacitor;

a second main pump capacitor coupled to the second secondary phase generator and the second preboot capacitor;

first and second main pump precharge capacitors coupled to one of the primary and secondary phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second p-channel gates coupled to the first and second main pump capacitors, respectively,

wherein the first main pump capacitor is prebooted to a first pre-determined level by the first preboot capacitor during the first phase, wherein the first pre-determined level moves to a second predetermined level during the second phase in response to the first primary phase generator, wherein the second predetermined level moves to a third predetermined level in response to the first secondary phase generator, and wherein the third predetermined level dumped to a first p-channel gate during the first phase, and

wherein the second main pump capacitor is prebooted to a first pre-determined level by the second preboot capacitor during the second phase, wherein the first predetermined level moves to a second pre-determined level during the first phase in response to the second primary phase generator, wherein the second predetermined level moves to a third predetermined level in response to the second secondary phase generator, and wherein the third predetermined level dumped to a second p-channel gate during the second phase, and wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second p-channel gates.

23. A charge pump circuit, comprising:

a phase generator to generate first and second phases during a phase cycle;

a primary phase generator, coupled to the phase generator, wherein the primary phase generator includes first and second phase generators to generate, first and second phase signals that are non-overlapping and crossing each other substantially around their high points during the phase cycle, wherein the primary phase generator further generates third and fourth phase signals that are non-overlapping and crossing around their low points during the phase cycle, and wherein the primary phase generator further generates seventh and eighth phase signals;

a secondary phase generator, coupled to the primary phase generator, wherein the secondary phase generator includes first and second secondary phase generators to generate fifth and sixth phase signals similar to the first and second phase signals, and including a predetermined delay from the first and second phase signals;

first and second main energy storing devices;

first and second main pump pre-charge capacitors coupled to one of the primary and secondary phase generators and coupled to the first and second main energy storing devices;

first and second pre-boosting stages, coupled to the first and second primary phase generators, respectively, wherein each of the first and second pre-boosting stages has an output, wherein the first and second pre-boosting stages boost the first and second main energy storing devices to a first predetermined boost level during the first and second phases respectively;

first and second pre-charging stages, coupled to the first and second main energy storing devices, wherein each of the first and second pre-charging stages has an output, and wherein the output of each of the first and second pre-charging stages is coupled to the output of the first and second pre-boosting stages, respectively; and

first and second gating devices coupled to the first and second main energy storing devices, respectively, wherein the first and second pre-charging stages further boost the first and second main energy storing devices to a second predetermined boost level during the first and second phases, respectively, wherein the first and second main energy storing devices are further boosted to a third predetermined boost level by the fifth and sixth phase signals to allow the first and second main energy storing devices to output a desired level of a high-voltage signal through the first and second gating devices during the first and second phases.

24. A two-phase integrated circuit charge pump, comprising:

an oscillator, where the oscillator generates an oscillating signal during a phase cycle including first and second phases;

a primary phase generator, coupled to the oscillator, wherein the primary phase generator generates first and second phase signals that are non-overlapping and crossing each other around high points of their signals during a phase cycle, further the primary phase generator generates third and fourth phase signals that are non-overlapping and crossing each other around low points of their signals during every phase cycle, and further the primary phase generator generates seventh and eighth phase signals;

a secondary phase generator, coupled to the primary phase generator, wherein the secondary phase generator receives the first and second phase signals and generates fifth and sixth phase signals, respectively, that are non-overlapping and crossing each other around high points of their signals during a phase cycle and includes a predetermined delay from the first and second phase signals;

first and second pre-boot precharge capacitors, coupled to the primary phase generator, wherein each of the first and second pre-boot precharge capacitors has an output, wherein the first and second pre-boot precharge capacitors receive the third and fourth phase signals from the primary phase generator during the first and second phases, respectively;

first and second pre-boot capacitors, coupled to the primary phase generator, wherein each of the first and second pre-boot capacitors has an output, wherein the output of each of the first and second pre-boot precharge capacitors is coupled to the output of the first and second preboot capacitors, respectively, receives the first and second phase signals from the primary phase generator respectively, and wherein the first and second pre-boot precharge capacitors pre-charges the first and second pre-boot capacitors to a pre-determined level during the first and second phases respectively;

first and second main pump precharge capacitors, coupled to the primary phase generator, wherein the first and second main pump precharge capacitors receive the seventh and eighth phase signals from the primary phase generator during the first and second phases respectively;

a first main pump capacitor, coupled to the first main pump precharge capacitor, the second pre-boot capacitor, and the secondary phase generator, wherein the first pre-boot capacitor pre-boots the first main pump to a predetermined booted level during the first phase, further the first main pump precharge capacitor precharges the first main pump capacitor to a second pre-determined level during the second phase and further the first main pump capacitor receives the fifth phase signal from the secondary phase generator during the first phase, and where the first main pump capacitor goes to a third predetermined level and outputs a charge through a first p-channel gate during the first phase; and

a second main pump capacitor, coupled to the second main pump precharge capacitor, the first pre-boot capacitor, and the secondary phase generator, wherein the second pre-boot capacitor pre-boots the second main pump to a predetermined booted level during the second phase, further the second main pump precharge capacitor precharges the second main pump capacitor to a second pre-determined level during the first phase, and further the second main pump capacitor receives the sixth phase signal from the secondary phase generator during the second phase, and where the second main pump capacitor goes to the third predetermined level and outputs the charge through a second p-channel gate during the second phase.

25. A two-phase charge pump for producing a pump voltage on an output line, comprising:

an oscillator, where the oscillator generates an oscillating signal;

a primary phase generator, coupled to the oscillator, generates first and second phase signals that are non-overlapping and crossing each other around high points of their signals during every phase cycle including first and second phases, further the primary phase generator generates third and fourth phase signals that are non-overlapping and crossing each other around low points of their signals during every phase cycle, and further the primary phase generator generates seventh and eighth phase signals;

a delay element, coupled to the primary phase generator, receives the first and second phase signals and generates fifth and sixth phase signals that are non-overlapping and crossing each other around high points of their signals during every phase cycle and includes a predetermined delay from the first and second phase signals;

a first and second pre-boot precharge circuitry, coupled to the primary phase generator, wherein the first and second pre-boot precharge circuitry has an output, receives the third and fourth signals from the primary phase generator during the first and second phases respectively;

a first and second pre-boot circuitry, coupled to the primary phase generator and the first and second pre-boot precharge capacitors respectively, wherein the first and second pre-boot circuitry has an output, wherein the output of the first and second pre-boot precharge circuitry is coupled to the output of the first and second pre-boot circuitry, receives the first and second phase signals from the primary phase generator respectively, and wherein the first and second pre-boot precharge circuitry pre-charges the first and second pre-boot capacitors to a pre-determined level during the first and second phases, respectively;

a first and second main pump precharge circuitry, coupled to the primary phase generator receives the seventh and eighth phase signals from the delay element during the first and second phases, respectively;

a first main pump circuitry, coupled to the first main pump precharge circuitry, the first pre-boot circuitry, and the delay element, where the first pre-boot circuitry pre-boots the first main pump circuitry to a predetermined booted level during the first phase, further the first main pump precharge circuitry precharges the first main pump circuitry to a second pre-determined level during the second phase and further the first main pump circuitry receives the fifth phase signal from the delay element during the first phase, and where the first main pump circuitry goes to a third predetermined level and outputs a charge through a first p-channel gate during the first phase; and

a second main pump circuitry, coupled to the second main pump precharge circuitry, the second pre-boot circuitry, and the delay element, where the second pre-boot circuitry pre-boots the second main pump to a predetermined booted level during the second phase, further the second main pump precharge circuitry precharges the second main pump circuitry to a second pre-determined level during the first phase, and further the second main pump circuitry receives the sixth phase signal from the delay element during the second phase, and wherein the second main pump circuitry goes to the third predetermined level and outputs the charge through a second p-channel gate during the second phase.

26. A charge pump circuit, comprising:

a phase generator to generate first and second phases, wherein the first phase is 180 degrees out of phase with respect to the second phase;

a primary phase generator, coupled to the oscillator, generates first and second phase signals that are non-overlapping and crossing each other around high points of their signals during every phase cycle including the first and second phases, further the primary phase generator generates third and fourth phase signals that are non-overlapping and crossing each other around low points of their signals during every phase cycle, and further the primary phase generator generates seventh and eighth phase signals;

a secondary phase generator, coupled to the primary phase generator, receives the first and second phase signals and generates fifth and sixth phase signals, respectively, that are non-overlapping and crossing each other around high points of their signals during every phase cycle and includes a predetermined delay from the first and second phase signals;

first and second pre-boot precharge capacitors, wherein each of the first and second pre-boot precharge capacitors has an output, coupled to the primary phase generator, receives the third and fourth signals from the primary phase generator during the first and second phases respectively;

first and second pre-boot capacitors, coupled to the primary phase generator, wherein each of the first and second pre-boot capacitors has an output, wherein the output of each of the first and second pre-boot precharge capacitors is coupled to the output of the first and second pre-boot capacitors, respectively, receives the first and second phase signals from the primary phase generator respectively, and wherein the first and second pre-boot precharge capacitors pre-charges the first and second pre-boot capacitors to a predetermined level during the first and second phases, respectively;

first and second main pump precharge capacitors, coupled to the primary phase generator receives the seventh and eighth phase signals from the primary phase generator during the first and second phases, respectively;

a first main pump capacitor, coupled to the first main pump precharge capacitor, the first pre-boot capacitor, and the secondary phase generator, where the first pre-boot capacitor pre-boots the first main pump to a predetermined booted level during the first phase, further the first main pump precharge capacitor precharges the first main pump capacitor to a second pre-determined level during the second phase and further the first main pump capacitor receives the fifth phase signal from the secondary phase generator during the first phase, and where the first main pump capacitor goes to a third predetermined level and outputs a charge through a first p-channel gate during the first phase; and

a second main pump capacitor, coupled to the second main pump precharge capacitor, the second pre-boot capacitor, and the secondary phase generator, where the second pre-boot capacitor pre-boots the second main pump to the predetermined booted level during the second phase, further the second main pump precharge capacitor precharges the second main pump capacitor to the second pre-determined level during the first phase, and further the second main pump capacitor receives the sixth phase signal from the secondary phase generator during the second phase, and where the second main pump capacitor goes to the third predetermined level and outputs the charge through a second p-channel gate during the second phase.

27. A memory device, comprising:

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

28. A memory device, comprising:

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively,

wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the second predetermined level moves to a third predetermined level in response to the plurality of phase generators during the first and second phases, respectively, and wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

29. A semiconductor die, comprising:

a substrate; and

an integrated circuit supported by the substrate, wherein the integrated circuit comprises at least one memory device, further wherein the at least one memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

30. A semiconductor die, comprising:

a substrate; and

an integrated circuit supported by the substrate, wherein the integrated circuit comprises at least one memory device, further wherein the at least one memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

31. A semiconductor die, comprising:

a substrate; and

an integrated circuit supported by the substrate, wherein the integrated circuit comprises at least one memory device, wherein the at least one memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively,

wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the second predetermined level moves to a third predetermined level in response to the plurality of phase generators during the first and second phases, respectively, and wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

32. A memory system, comprising:

a controller;

a command link coupled to the controller;

a data link coupled to the controller; and

a memory device coupled to the command link and the data link, wherein the memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

33. A memory system, comprising:

a controller;

a command link coupled to the controller;

a data link coupled to the controller; and

a memory device coupled to the command link and the data link, wherein the memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively,

wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the second predetermined level moves to a third predetermined level in response to the plurality of phase generators during the first and second phases, respectively, and wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

34. An electronic system, comprising:

a processor; and

at least one memory device coupled to the processor, wherein the at least one memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

35. An electronic system, comprising:

a processor; and

at least one memory device coupled to the processor, wherein the at least one memory device comprises;

a plurality of phase generators;

first and second preboot capacitors coupled to the plurality of phase generators, wherein each of the first and second preboot capacitors has an output;

first and second main pump capacitors coupled to the plurality of phase generators, and the first and second preboot capacitors, respectively;

first and second main pump precharge capacitors coupled to the plurality of phase generators and coupled to the first and second main pump capacitors, respectively;

first and second pre-boot pre-charge capacitors, wherein each of the first and second pre-boot pre-charge capacitors has an output, and wherein the output of each of the first and second pre-boot pre-charge capacitors is coupled to the output of the first and second preboot capacitors, respectively; and

first and second gating devices coupled to the first and second main pump capacitors, respectively,

wherein the first and second main pump capacitors are prebooted to a first predetermined level by the first and second preboot capacitors during first and second phases, respectively, wherein the first predetermined level moves to a second predetermined level in response to the plurality of phase generators during the first and second phases, respectively, wherein the second predetermined level moves to a third predetermined level in response to the plurality of phase generators during the first and second phases, respectively, and wherein the third predetermined level is dumped to the first and second gating devices, during the first and second phases, respectively, wherein the first and second main pump capacitors output a pump voltage higher than a supply voltage through the first and second gating devices.

36. A method of producing a pump supply voltage from an integrated circuit two phase charge pump, comprising:

pre-charging a pre-boot capacitor to a first pre-determined level during a first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level during a second phase;

pre-charging a first main pump capacitor to a second pre-determined level during the second phase;

boosting the first main pump to a third pre-determined level during the first phase;

outputting the first main pump charge to a Vccp during the first phase through a first gating device;

pre-charging the second main pump capacitor to the second pre-determined level during the first phase;

boosting the second main pump to the third pre-determined level during the second phase; and

outputting the second main pump charge to the Vccp during the second phase through a second gating device.

37. A method of producing a pump supply voltage from an integrated circuit two phase charge pump, comprising:

pre-charging a pre-boot capacitor to a first pre-determined level during a first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level during a second phase;

pre-charging a first main pump capacitor to a second pre-determined level during the second phase;

boosting the first main pump to a third pre-determined level during the first phase;

outputting the first main pump charge to a Vccp through a first p-channel gate during the first phase;

pre-charging the second main pump capacitor to the second pre-determined level during the first phase;

boosting the second main pump to the third pre-determined level during the second phase; and

outputting the second main pump charge to the Vccp through a second p-channel gate during the second phase.

38. A method of producing a pump supply voltage from an integrated circuit two phase charge pump, comprising:

pre-charging a pre-boot capacitor to a first pre-determined level during a first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level during a second phase;

pre-charging a first main pump capacitor to a second pre-determined level during the second phase;

boosting the first main pump to a third pre-determined level during the first phase;

outputting the first main pump charge to a Vccp through a first p-channel gate during the first phase;

pre-charging the second main pump capacitor to the second pre-determined level during the first phase;

boosting the second main pump to the third pre-determined level during the second phase; and

outputting the second main pump charge to the Vccp through a second p-channel gate during the second phase.

39. A method of producing a pump supply voltage from an integrated circuit two phase charge pump, comprising:

generating signals that are non-overlapping and crossing each other around high points of their signals;

generating signals that are non-overlapping and crossing each other around low points of their signals;

generating signals having a predetermined delay from the signals that are non-overlapping and crossing each other around high points;

pre-charging a first pre-boot capacitor to a first pre-determined level using the signals that are non-overlapping and crossing around the high points of their signals during a first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level using the signals that are non-overlapping and crossing around the low points of their signals during a second phase;

pre-charging the first main pump capacitor to a second pre-determined level by the signals that are non-overlapping and crossing around the low points of their signals during the second phase;

inputting the signals having a predetermined delay to boost the first main pump to a third pre-determined level during the first phase;

outputting the first main pump charge to a first p-channel gate during the first phase;

outputting the charge from the first channel gate to a Vccp;

pre-charging the second main pump capacitor to the second pre-determined level by the signals that are non-overlapping and crossing around the low points of their signals during the first phase;

inputting the signals having a predetermined delay to boost the second main pump to the third pre-determined level during the second phase;

outputting the second main pump charge to a second p-channel gate during the second phase; and

outputting the charge from the second p-channel gate to the V_ccp.

40. A method of producing a pump supply voltage from an integrated circuit two phase charge pump, comprising:

generating an oscillating signal;

generating a first and second phase signals that are non-overlapping and crossing each other around high points of their signals during every phase cycle from the oscillating signal by a primary phase generator;

generating a third and fourth phase signals that are non-overlapping and crossing each other around low points of their signals during every phase cycle from the oscillating signal by the primary phase generator;

generating a fifth and sixth phase signals having a predetermined delay from the first and second phase signals that are non-overlapping and crossing each other around high points from the first and second phase signals received from the primary phase generator by a secondary phase generator;

generating a seventh and eighth phase signals by the primary phase generator;

pre-charging a first pre-boot capacitor to a first pre-determined level using the first and third phase signals during the first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level using the second and fourth phase signals during the second phase;

pre-booting a first main pump capacitor to the first pre-determined boot level by the first pre-boot capacitor during the first phase;

pre-booting a second main pump capacitor to the pre-determined boot level by the second pre-boot capacitor during the second phase;

pre-charging the first main pump capacitor to a second pre-determined level by the seventh phase signal during the second phase;

inputting the fifth phase signal to boost the first main pump to a third pre-determined level during the first phase;

outputting the first main pump charge to a first p-channel gate during the first phase;

outputting the charge from the first p-channel gate to a Vccp;

pre-charging the second main pump capacitor to the second pre-determined level by the eight phase signal during the first phase;

inputting the sixth phase signal to boost the second main pump to the third pre-determined level during the second phase;

outputting the second main pump charge to a second p-channel gate during the second phase; and

outputting the charge from the second p-channel gate to the Vccp.

41. A method of producing a pump supply voltage from an integrated circuit two phase charge pump, comprising:

generating an oscillating signal;

generating a first and second phase signals that are non-overlapping and crossing each other around high points of their signals during every phase cycle from the oscillating signal by a primary phase generator;

generating a third and fourth phase signals that are non-overlapping and crossing each other around low points of their signals during every phase cycle from the oscillating signal by the primary phase generator;

generating a fifth and sixth phase signals having a predetermined delay of approximately in the range of about 10 to 30 nanoseconds from the first and second phase signals that are non-overlapping and crossing each other around high points from the first and second phase signals received from the primary phase generator by a secondary phase generator;

generating a seventh and eighth phase signals by the primary phase generator;

pre-charging a first pre-boot capacitor to a first pre-determined level of approximately in the range of about 1 to 5 volts using the first and third phase signals during the first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level of approximately in the range of about 1 to 5 volts using the second and fourth phase signals during the second phase;

pre-booting a first main pump capacitor to the first pre-determined boot level of approximately in the range of about 1 to 5 volts by the first pre-boot capacitor during the first phase;

pre-booting a second main pump capacitor to the pre-determined boot level of approximately in the range of about 1 to 5 volts by the second pre-boot capacitor during the second phase;

pre-charging the first main pump capacitor to a second pre-determined level of approximately in the range of about 1 to 5 volts by the seventh phase signal during the second phase;

inputting the fifth phase signal to boost the first main pump to a third pre-determined level of approximately in the range of about 1 to 5 volts during the first phase;

outputting the first main pump charge to a first p-channel gate during the first phase;

outputting the charge from the first p-channel gate to a Vccp;

pre-charging the second main pump capacitor to the second pre-determined level approximately in the range of about 1 to 5 volts by the eight phase signal during the first phase;

inputting the sixth phase signal to boost the second main pump to the third pre-determined level of approximately in the range of about 1 to 5 volts during the second phase;

outputting the second main pump charge to a second p-channel gate during the second phase; and

outputting the charge from the second p-channel gate to the Vccp.

42. A method of producing a pump supply voltage in an integrated circuit, the method, comprising:

generating an oscillating signal;

generating a first and second phase signals that are non-overlapping and crossing each other around high points of their signals during every phase cycle from the oscillating signal by a primary phase generator;

generating a third and fourth phase signals that are non-overlapping and crossing each other around low points of their signals during every phase cycle from the oscillating signal by the primary phase generator;

generating a fifth and sixth phase signals from the first and second phase signals, where the fifth and sixth phase signals are similar to the first and second phase signals, and having a predetermined delay from the first and second phase signals by a secondary phase generator;

generating a seventh and eighth phase signals by the primary phase generator;

pre-charging a first pre-boot capacitor to a first pre-determined level using the first and third phase signals during the first phase;

pre-charging a second pre-boot capacitor to the first pre-determined level using the second and fourth phase signals during the second phase;

pre-booting a first main pump capacitor to the first pre-determined boot level by the first pre-boot capacitor during the first phase;

pre-booting a second main pump capacitor to the pre-determined boot level by the second pre-boot capacitor during the second phase;

pre-charging the first main pump capacitor to a second pre-determined level by the seventh phase signal during the second phase;

inputting the fifth phase signal to raise the first main pump to a third pre-determined level during the first phase;

outputting the first main pump charge to a Vccp through a first gating device during the first phase;

pre-charging the second main pump capacitor to the second pre-determined level by the eight phase signal during the first phase;

inputting the sixth phase signal to raise the second main pump to the third pre-determined level during the second phase; and

outputting the second main pump charge to the Vccp through a second gating device during the second phase.