Overlay inspection apparatus for semiconductor substrate and method thereof

• US 6,801,827 B2
• Filed: 10/09/2002
• Issued: 10/05/2004
• Est. Priority Date: 07/17/2001
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsumoto, Shunichi, Yoshitake, Yasuhiro, Miwa, Toshiharu
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): KASENGE, CHARLES R
• Application Number:
  US10/268,716
• Publication Number:
  US 20030033046A1
• Time in Patent Office: 727 Days
• Field of Search: 700/121, 700/124, 438/14, 438/669, 365/400, 365/401, 716/21
• US Class Current: 700/121
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70525 Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
• CPC Class Codes: G03F 7/706 Aberration measurement
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring

Abstract

A system for manufacturing a semiconductor device which predicts a difference in registration error between a circuit pattern and an overlay mark from a pattern dimension, illumination conditions and the wave aberration of an exposure lens, feeds a correction value based on the predicted difference back to an exposure device and modifies an overlay inspection data control limit.

Claims

1. A method for correcting a lateral registration error between semiconductor device manufacturing steps, the method comprising:

reading a dimension of a circuit pattern in a first layer formation process;

reading a dimension of an overlay mark in said first layer formation process;

reading illumination conditions in an exposure device in said first layer formation process;

reading a wave aberration corresponding to said circuit pattern in the exposure device in said first layer formation process;

reading a wave aberration corresponding to said overlay mark in said first layer formation process;

calculating projection images of said circuit pattern and said overlay mark in said first layer formation process;

reading a dimension of a circuit pattern in a second layer formation process;

reading a dimension of an overlay mark in said second layer formation process;

reading illumination conditions in an exposure device in said second layer formation process;

reading a wave aberration corresponding to said circuit pattern in the exposure device in said second layer formation process;

reading a wave aberration corresponding to said overlay mark in said second layer formation process;

calculating projection images of said circuit pattern and said overlay mark in said second layer formation process;

calculating a registration error between the projection image of the circuit pattern in said first layer formation process and the projection image of the circuit pattern in said second layer formation process as well as a registration error between the projection image of the overlay mark in said first layer formation process and the projection image of the overlay mark in said second layer formation process;

finding a relationship between the registration error of the projection image of said circuit pattern and the registration error of the projection image of said overlay mark;

measuring a registration error between the overlay marks formed on a substrate of a semiconductor device by the first layer formation process and the second layer formation process;

predicting a registration error of the circuit patterns formed on the substrate of the semiconductor device by the first layer formation process and the second layer formation process, by using information of said measured registration error of the overlay marks and said calculated registration error; and

feeding back said predicted registration error of the circuit patterns to the exposure device of said second layer formation process as a correction value.

2. The method as set forth in claim 1, wherein said circuit pattern is a circuit pattern having the smallest shift allowable value among the circuit patterns in the first and second layer formation processes.

3. A method for correcting a lateral registration error between semiconductor device manufacturing steps, the method comprising:

calculating a registration error between an image of a first circuit pattern formed when a circuit pattern of a first layer formation process is transferred with use of a first exposure device and an image of a second circuit pattern formed when a circuit pattern of a second layer formation process is transferred onto the image of said first circuit pattern with use of a second exposure device;

calculating a registration error between an image of a first overlay mark formed when an overlay mark of said first layer formation process is transferred with use of said first exposure device and an image of a second overlay mark formed when an overlay mark of said second layer formation process is transferred with use of said second exposure device;

determining a relationship between said calculated registration error between the transferred images of said first and second circuit patterns and said calculated registration error between the images of said first and second overlay marks;

measuring a registration error between a transferred image formed when said first overlay mark is transferred with use of said first exposure device and a transferred image formed when said second overlay mark is transferred with use of said second exposure device;

predicting a registration error between transferred images of actual circuit patterns from said measured registration error with use of said determined relationship between said calculated registration errors of said circuit patterns and overlay marks; and

determining a correction of the exposure device of said second layer formation process from said predicted registration error between the transferred images of the actual circuit patterns and feeding said correction back to the exposure device of said second layer formation process.

4. A method for inspecting a semiconductor substrate, the method comprising:

calculating registration errors between transfer images of first and second overlay marks and circuit patterns when the first overlay mark and circuit pattern are transferred on a substrate with use of a first exposure device and when the second overlay marks and circuit patterns are transferred on the substrate with use of a second exposure device, the projection images obtained by the second exposure device being transferred onto said substrate at an area where said first overlay mark and circuit pattern are transferred;

determining a relationship between said calculated registration error between the transfer images of the overlay marks and said calculated registration error between the transfer images of the circuit patterns;

measuring an actual registration error between the transfer images of the first and second overlay marks formed when said first overlay mark is actually transferred with use of the first exposure device and when said second overlay mark is actually transferred with use of the second exposure device;

predicting a registration error between the transfer images of the circuit patterns using data relating to said measured registration error, said determined relationship between the registration errors of the circuit patterns and the registration errors of the overlay marks;

determining a correction value of the exposure device in said second layer formation process from said predicted registration error between the transfer images of the circuit patterns;

correcting said second exposure device on the basis of said determined correction value; and

subjecting the second circuit pattern by said corrected second exposure device to light exposure on the first circuit pattern subjected to light exposure by said first exposure device.

5. The method as set forth in claim 4, wherein said registration error between the transfer images of the circuit patterns is calculated with use of information on a dimension of the first circuit pattern and on a dimension of the second circuit pattern to be formed on said first circuit pattern, information on illumination conditions of the first exposure device for light exposure of said first circuit pattern and on illumination conditions of the second exposure device for light exposure of said second circuit pattern, and information on a wave aberration of said first exposure device and on a wave aberration of said second exposure device.

6. A method for inspecting a substrate, the method comprising:

calculating a relationship between a registration error between projection images of first and second circuit patterns and a registration error between projection images of first and second overlay marks with use of information on a dimension of said first circuit pattern and a dimension of said second circuit pattern to be formed on said first circuit pattern, information on illumination conditions of the first exposure device for light exposure of said first circuit pattern and on illumination conditions of the second exposure device for light exposure of said second circuit pattern, and information on a wave aberration of said first exposure device and on a wave aberration of said second exposure device;

measuring an actual registration error between a projection image formed when said first overlay mark is actually transferred with use of said first exposure device and a projection image formed when said second overlay mark is actually transferred with use of said second exposure device;

predicting an actual registration error between the projection images of the circuit patterns from data about said actual registration error between the projection images of the overlay marks with use of said calculated relationship between the registration errors between the projection images of the circuit patterns and overlay marks;

correcting said exposure device of a second layer formation process on the basis of a correction corresponding to said predicted actual registration error between the projection images of the circuit patterns; and

subjecting said second circuit pattern by said corrected second exposure device to light exposure on said first circuit pattern subjected by said first exposure device to light exposure.

7. The method as set forth in claim 6, wherein, in said step of correcting the exposure device of said second layer formation process, the exposure device of said second layer formation process is corrected by feeding a correction corresponding to said predicted actual registration error between the projection images of the circuit patterns back to the exposure device of said second layer formation process.

8. The method as set forth in claim 6, wherein, in said step of correcting the exposure device of said second layer formation process, the exposure device of said first layer formation process is corrected on the basis of a correction corresponding to said predicted actual registration error between the projection images of the circuit patterns.

9. A method for inspecting a substrate, the method comprising:

measuring an actual registration error between a projection image formed when a first overlay mark formed on a first reticle is actually transferred on a substrate with use of a first exposure device and a projection image formed when a second overlay mark formed on a second reticle is actually transferred on said substrate with use of a second exposure device;

predicting an actual registration error between the projection images of the actual circuit patterns from data on said measured registration error between the projection images of the overlay marks with use of a relationship between a projection image formed when a first circuit pattern formed on said first reticle is transferred on said substrate with use of said first exposure device and a projection image formed when a second circuit pattern formed on said second reticle is transferred on the substrate with use of said second exposure device and said registration error between the projection images of the overlay marks;

correcting said second exposure device on the basis of information on said predicted actual registration error between the projection images of the circuit patterns; and

subjecting said second circuit pattern by said corrected second exposure device to light exposure on said first circuit pattern subjected by said first exposure device to light exposure.

10. The method as set forth in claim 9, wherein, in said step of correcting said second exposure device, said second exposure device is corrected by feeding a correction corresponding to said predicted actual registration error between the projection images of the circuit patterns back to said second exposure device.

11. The method as set forth in claim 9, wherein, in said step of correcting said second exposure device, said first exposure device is also corrected on the basis of a correction corresponding to said predicted actual registration error between the projection images of the circuit patterns.

12. A method for inspecting a substrate, the method comprising:

measuring a registration error between a first transferred image of a first pattern formed on or over the substrate when a first overlay mark formed on a first reticle is transferred to the substrate with use of a first exposure device and a second transferred image of a second pattern formed over the first pattern when a second overlay mark formed on a second reticle is transferred to said substrate with use of a second exposure device;

predicting a registration error between third and fourth images of first and second circuit patterns associated with the substrate using data on said measured registration error; and

adjusting said second exposure device using said predicted registration error between the third and fourth images of the first and second circuit patterns.

13. The method of claim 12, further comprising:

using said adjusted second exposure device to transfer said second circuit pattern to said substrate.