Switch circuit and method of switching radio frequency signals

• US 6,804,502 B2
• Filed: 10/08/2002
• Issued: 10/12/2004
• Est. Priority Date: 10/10/2001
• Status: Expired due to Term

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Cable, James S.
• Primary Examiner(s): TIEU, BINH KIEN
• Application Number:
  US10/267,531
• Publication Number:
  US 20030090313A1
• Time in Patent Office: 735 Days
• Field of Search: 455/425, 455/26.1, 455/78, 455/550.1, 455/556.1, 455/560, 455/333, 257/341, 257/280, 257/281, 257/472
• US Class Current: 455/333
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 2017/0803 against radiation hardening
• CPC Class Codes: H04B 1/40 Circuits

Abstract

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.

Claims

1. An RF switch circuit for switching RF signals, comprising:

(a) a first input port receiving a first RF input signal;

(b) a second input port receiving a second RF input signal;

(c) an RF common port;

(d) a first switch transistor grouping having a first node coupled to the first input port and a second node coupled to the RF common port, wherein the first switch transistor grouping is controlled by a switch control signal (SW);

(e) a second switch transistor grouping having a first node coupled to the second input port and a second node coupled to the RF common port, wherein the second switch transistor grouping is controlled by an inverse (SW_) of the switch control signal (SW);

(f) a first shunt transistor grouping having a first node coupled to the second input port and a second node coupled to ground, wherein the first shunt transistor grouping is controlled by the switch control signal (SW); and

(g) a second shunt transistor grouping having a first node coupled to the first input port and a second node coupled to ground, wherein the second shunt transistor grouping is controlled by the inverse (SW_) of the switch control signal (SW);

wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground; and

wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground.

2. The RF switch circuit of claim 1, wherein the switch circuit is fabricated in a silicon-on-insulator (SOI) technology.

3. The RF switch circuit of claim 1, wherein the switch circuit is fabricated on an Ultra-Thin-Silicon (“

UTSi”

) substrate.

4. The RF switch circuit of claim 3, wherein the transistor groupings comprise MOSFET transistors formed in a thin silicon layer on a fully insulating sapphire wafer, and wherein the fully insulating sapphire wafer enhances performance characteristics of the RF switch by reducing substrate coupling effects.

5. The RF switch circuit of claim 4, wherein switch insertion loss is reduced by reducing on-resistances of the MOSFET transistors.

6. The RF switch circuit of claim 4, wherein switch isolation characteristics of the RF switch is improved by reducing parasitic capacitance between nodes of the MOSFET transistors.

7. The RF switch circuit of claim 3, wherein the transistor groupings comprise a plurality of MOSFET transistors arranged in a stacked configuration.

8. The RF switch circuit of claim 7, wherein the stacked MOSFET transistors include gate nodes coupled to respective and associated gate resistors, and wherein the gate resistors are commonly controlled by a switching voltage.

9. The RF switch circuit of claim 8, wherein the gate resistors coupled to the transistor gate nodes of the first switch and shunt transistor groupings are commonly controlled by the switch control signal SW.

10. The RF switch circuit of claim 8, wherein the gate resistors coupled to the transistor gate nodes of the second switch and shunt transistor groupings are commonly controlled by the inverse switch control signal SW_.

11. The RF switch circuit of claim 8, wherein the MOSFET transistors have associated gate capacitance, wherein RC time constants associated with each MOSFET transistor within the transistor groupings are functions of the gate resistors and the associated gate capacitance, and wherein the RC time constant of each transistor far exceeds a period of the RF input signals thereby causing RF voltages to be shared equally across the MOSFET transistors.

12. The RF switch circuit of claim 8, wherein a breakdown voltage across the plurality of stacked MOSFET transistors of a selected transistor grouping is effectively increased to n times a breakdown voltage of an individual MOSFET transistor in the selected transistor grouping, wherein n comprises the total number of MOSFET transistors in the selected transistor grouping.

13. The RF switch circuit of claim 12, wherein the switch circuit has an associated 1 dB compression point, and wherein the 1 dB compression point is increased using the stacked MOSFET transistor configuration.

14. The RF switch circuit of claim 7, wherein the first and second RF input signals have associated input power levels, and wherein increased input power levels can be accommodated by the RF switch circuit by increasing the number of MOSFET transistors per transistor grouping.

15. The RF switch circuit of claim 7, wherein the first and second RF input signals have associated input power levels, and wherein increased input power levels can be accommodated by the RF switch circuit by varying the physical size of the transistors used in implementing the transistor groupings.

16. A fully integrated RF switch circuit, comprising:

(a) the RF switch circuit as set forth in claim 3;

(b) a control logic block, coupled to the RF switch circuit, wherein the control logic block outputs the switch control signal (SW) and the inverse switch control signal (SW_); and

(c) a negative voltage generator, coupled to the control logic block, wherein the negative voltage generator receives a clocking input signal and a positive power supply voltage from an external power supply, and wherein the negative voltage generator outputs a negative power supply voltage.

17. The fully integrated RF switch circuit of claim 16, wherein the RF switch circuit is integrated in an integrated circuit (IC) with a plurality of digital and analog circuits.

18. The fully integrated RF switch circuit of claim 16, further including:

(a) an oscillator, wherein the oscillator outputs clocking input signals;

(b) a charge pump, coupled to the oscillator, wherein the oscillator inputs the clocking input signals, and wherein the charge pump outputs a negative power supply voltage;

(c) a logic circuit block, coupled to the charge pump, wherein the logic circuit block outputs control signals for use in controlling the switch and shunt transistor groupings;

(d) a level-shifting circuit, coupled to the logic circuit block and the RF switch circuit, wherein the level-shifting circuit reduces gate-to-drain, gate-to-source, and drain-to-source voltages of MOSFET transistors used to implement the transistor groupings; and

(e) an RF buffer circuit, coupled to the RF switch circuit, wherein the RF buffer circuit isolates RF signal energy from the charge pump and the logic circuit blocks.

19. The fully integrated RF switch circuit of claim 18, wherein the charge pump comprises:

(a) at least two P-channel MOSFET transistors;

(b) at least two N-channel MOSFET transistors, wherein each N-channel MOSFET transistor is coupled in series with a respective and associated P-channel MOSFET transistor thereby forming a respective leg of the charge pump;

(c) at least one coupling capacitor coupling each leg of the charge pump coupled to a successive leg; and

(d) an output capacitor, coupled to an output leg of the charge pump;

wherein the negative power supply voltage is generated by the charge pump by alternately charging and discharging the coupling and output capacitors using non-overlapping input clocking signals to drive the P-channel and N-channel MOSFET transistors.

20. The fully integrated RF switch circuit of claim 19, wherein the non-overlapping input clocking signals comprise two non-overlapping clock control signals, and wherein a first non-overlapping clock control signal controls the P-channel transistors, and wherein a second non-overlapping clock control signal controls the N-channel transistors.

21. The fully integrated RF switch circuit of claim 19, wherein the P-channel and N-channel transistors are single-threshold transistors.

22. The fully integrated RF switch circuit of claim 19, wherein the non-overlapping input clocking signals are generated by a pulse shift circuit.

23. The fully integrated RF switch circuit of claim 19, wherein the non-overlapping input clocking signals are derived from the oscillator clocking input signals.

24. The fully integrated RF switch circuit of claim 19, wherein the oscillator comprises a relaxation oscillator.

25. The fully integrated RF switch circuit of claim 19, wherein the non-overlapping input clocking signals vary in voltage amplitude from −

Vdd to +Vdd.

26. The fully integrated RF switch circuit of claim 18, wherein the level-shifting circuit comprises a plurality of inverters coupled together in a feedback configuration.

27. The fully integrated RF switch circuit of claim 26, wherein the inverters comprise differential inverters having a first differential input, a second differential input, a logic input and a logic output, and wherein the level-shifting circuit comprises:

(a) an input inverter group comprising two input differential inverters, wherein a first input differential inverter receives a logic input signal (input) and outputs a first logic input signal (in), and wherein a second input differential inverter receives the first logic input signal (in) and outputs an inverse (in_) of the first logic input signal;

(b) a first inverter group comprising three differential inverters, wherein the logic output of a first inverter of the first inverter group is coupled to the first logic input signal (in), the logic output of the first inverter is coupled to a first differential input of an output inverter of the first inverter group, the logic output of a second inverter of the first inverter group is coupled to a second differential input of the output inverter of the first inverter group, and wherein the output inverter of the first inverter group outputs a first output signal (out); and

(c) a second inverter group comprising three differential inverters, wherein the logic output of a first inverter of the second inverter group is coupled to the inverse (in_) of the first logic input signal, the logic output of the first inverter of the second inverter group is coupled to a first differential input of an output inverter of the second inverter group, the logic output of a second inverter of the second inverter group is coupled to a second differential input of the output inverter of the second inverter group, and wherein the output inverter of the second inverter group outputs a second output signal (out_);

wherein the first output signal (out) is provided as feedback and input to the logic input of the second inverter of the second inverter group, and wherein the second output signal (out_) is provided as feedback and input to the logic input of the second inverter of the first inverter group.

28. The fully integrated RF switch circuit of claim 27, wherein the first and second output signals control the switch and shunt transistor groupings of the RF switch.

29. The fully integrated RF switch circuit of claim 26, wherein the level-shifting circuit shifts the DC level of the logic input signal (input) without affecting the frequency response of the input signal.

30. The fully integrated RF switch circuit of claim 18, wherein the RF buffer circuit comprises a two-stage circuit comprising a first-stage level-shifting circuit and a second stage RF buffer circuit, and wherein the first stage level-shifting circuit comprises the level-shifting circuit defined by claim 27, and wherein the second stage RF buffer circuit comprises a second plurality of differential inverters, wherein the second plurality of differential inverters each have a first differential input, a second differential input, a logic input and a logic output, wherein the second stage RF buffer circuit further comprises:

(a) a first RF buffer inverter group comprising three differential inverters, wherein the logic inputs of a first and second inverters of the first RF buffer inverter group are coupled to the first output signal (out) output by the level-shifting circuit, the logic output of the first inverter of the first RF buffer inverter group is coupled to a first differential input of an output inverter of the first RF buffer inverter group, the logic output of the second inverter of the first RF buffer inverter group is coupled to a second differential input of the output inverter of the first RF buffer inverter group, and wherein the output inverter of the first RF buffer inverter group outputs a first output signal (OUT); and

(b) a second RF buffer inverter group comprising three differential inverters, wherein the logic inputs of a first and second inverters of the second RF buffer inverter group are coupled to the second output signal (out ₁₃ ) output by the level-shifting circuit, the logic output of the first inverter of the second RF buffer inverter group is coupled to a first differential input of an output inverter of the second RF buffer inverter group, the logic output of the second inverter of the second RF buffer inverter group is coupled to a second differential input of the output inverter of the second RF buffer inverter group, and wherein the output inverter of the second RF buffer inverter group outputs a second output signal (OUT_).

31. The fully integrated RF switch circuit of claim 30, wherein the RF buffer circuit isolates digital logic signals from the RF switch circuit.

32. The fully integrated RF switch circuit of claim 31, wherein the second stage RF buffer circuit provides no feedback of the output signals OUT and OUT_ to the first stage level-shifting circuit thereby providing improved isolation of the RF switch from the digital logic signals.

33. The fully integrated RF switch circuit of claim 30, wherein transistors used to implement the first stage level-shifting circuit are smaller than transistors used to implement the second stage RF buffer circuit.

34. The fully integrated RF switch circuit of claim 27, further including a voltage divider circuit coupled to the output signals (out) and (out_), wherein the voltage divider circuit limits the voltage levels of the output signals before they are provided as feedback to the second inverters of the first and second inverter groups.

35. The fully integrated RF switch circuit of claim 34, wherein the voltage divider limits the voltage levels to approximately Vdd.

36. The fully integrated RF switch circuit of claim 34, wherein the voltage divider comprises a plurality of MOSFET devices coupled together in a serial configuration, wherein an output MOSFET device is coupled to a ground node through a ballast resistor, and wherein the MOSFET devices implement a diode function.

37. The fully integrated RF switch circuit of claim 18, wherein the RF buffer circuit comprises a two-stage circuit comprising a first-stage level-shifting circuit and a second stage RF buffer circuit, and wherein the first stage level-shifting circuit comprises the level-shifting circuit defined by claim 34, and wherein the second stage RF buffer circuit comprises a second plurality of differential inverters, wherein the second plurality of differential inverters each have a first differential input, a second differential input, a logic input and a logic output, wherein the second stage RF buffer circuit further comprises:

(a) a first RF buffer inverter group comprising three differential inverters, wherein the logic input of a first inverter of the first RF buffer inverter group is coupled to a first output signal (out_pos1) output by the level-shifting circuit, the logic input of a second inverter of the first RF buffer inverter group is coupled to a second output signal (out_neg1) output by the level-shifting circuit, the output of the first inverter of the first RF buffer inverter group is coupled to a first differential input of an output inverter of the first RF buffer inverter group, the logic output of the second inverter of the first RF buffer inverter group is coupled to a second differential input of the output inverter of the first RF buffer inverter group, and wherein the output inverter of the first RF buffer inverter group outputs a first output signal (OUT); and

(b) a second RF buffer inverter group comprising three differential inverters, wherein the logic input of a first inverter of the second RF buffer inverter group is coupled to a third output signal (out_pos2) output by the level-shifting circuit, the logic input of a second inverter of the second RF buffer inverter group is coupled to a fourth output signal (out_neg2) output by the level-shifting circuit, the output of the first inverter of the second RF buffer inverter group is coupled to a first differential input of an output inverter of the second RF buffer inverter group, the logic output of the second inverter of the second RF buffer inverter group is coupled to a second differential input of the output inverter of the second RF buffer inverter group, and wherein the output inverter of the second RF buffer inverter group outputs a second output signal (OUT_);

and wherein the first output signal (out_pos1) comprises a buffered output of the first inverter of the first inverter group of the level-shifting circuit, the second output signal (out_neg1) comprises a buffered output of the second inverter of the first inverter group of the level-shifting circuit, the third output signal (out_pos2) comprises a buffered output of the first inverter of the second inverter group of the level-shifting circuit, and the fourth output signal (out_neg2) comprises a buffered output of the second inverter of the second inverter group of the level-shifting circuit.

38. The fully integrated RF switch circuit of claim 20, wherein the non-overlapping input clocking signals are input to level-shifting circuits defined by claim 34 before being input to the charge pump.

39. The fully integrated RF switch circuit of claim 38, wherein the level-shifting circuits comprise a first and a second level-shifting circuit, wherein the first and second level-shifting circuits are defined by claim 34, and wherein the first level-shifting circuit outputs a first output signal (clk1pos) from the logic output of the first inverter in its first inverter group, a second output signal (clk1neg) from the logic output of the second inverter in its first inverter group, a third output signal (clk1pos_) from the logic output of the first inverter in its second inverter group, and a fourth output signal (clk1neg_) from the logic output of the second inverter in its second inverter group, and wherein the second level-shifting circuit outputs a fifth output signal (clk2pos) from the logic output of the first inverter in its first inverter group, a sixth output signal (clk2neg) from the logic output of the second inverter in its first inverter group, a seventh output signal (clk2pos_) from the logic output of the first inverter in its second inverter group, and an eighth output signal (clk2neg_) from the logic output of the second inverter in its second inverter group.

40. The fully integrated RF switch circuit of claim 39, wherein the third output signal (clk1pos_) controls a first P-channel MOSFET transistor of the charge pump, the fourth output signal (clk1neg_) controls a second P-channel MOSFET transistor of the charge pump, the fifth output signal (clk2pos) controls a first N-channel MOSFET transistor associated with the first P-channel MOSFET transistor, and the sixth output signal (clk2neg) controls a second N-channel MOSFET transistor associated with the second P-channel MOSFET transistor.

41. An RF switch circuit switching RF signals, comprising:

(a) a first input means for receiving a first RF input signal;

(b) a second input means for receiving a second RF input signal;

(c) an RF common port means;

(d) a first stacked transistor switching means having a first node coupled to the first input means and a second node coupled to the RF common port means, wherein the first stacked transistor switching means is controlled by a switch control signal (SW);

(e) a second stacked transistor switching means having a first node coupled to the second input means and a second node coupled to the RF common port means, wherein the second stacked transistor switching means is controlled by an inverse (SW_) of the switch control signal (SW);

(f) a first stacked transistor shunting means having a first node coupled to the second input means and a second node coupled to ground, wherein the first stacked transistor shunting means is controlled by the switch control signal (SW); and

(g) a second stacked transistor shunting means having a first node coupled to the first input means and a second node coupled to ground, wherein the second stacked transistor shunting means is controlled by the inverse (SW_) of the switch control signal (SW);

wherein, when SW is enabled, the first stacked transistor switching means and first stacked transistor shunting means are enabled while the second stacked transistor switching and the second stacked transistor shunting means are disabled, thereby passing the first RF input signal through to the RF common port means and shunting the second RF input signal to ground; and

wherein when SW is disabled, the second stacked transistor switching means and the second stacked transistor shunting means are enabled while the first stacked transistor switching and first stacked transistor shunting means are disabled, thereby passing the second RF input signal through to the RF common port means and shunting the first RF input signal to ground.

42. A method of switching RF signals, comprising:

(a) inputting a first RF input signal to a first switch transistor grouping and a first shunt transistor grouping, wherein the transistor groupings comprise a plurality of stacked transistors;

(b) inputting a second RF input signal to a second switch transistor grouping and a second shunt transistor grouping, wherein the transistor groupings comprise a plurality of stacked transistors;

(c) enabling the first switch transistor grouping while disabling the first shunt transistor grouping, and simultaneously disabling the second switch transistor grouping while enabling the second shunt transistor grouping, thereby passing the first RF input signal and shunting the second RF input signal; and

(d) enabling the second switch transistor grouping while disabling the second shunt transistor grouping, and simultaneously disabling the first switch transistor grouping while enabling the first shunt transistor grouping, thereby passing the second RF input signal and shunting the first RF input signal.