Structure and method for monitoring a semiconductor process, and method of making such a structure

• US 6,808,944 B1
• Filed: 07/24/2000
• Issued: 10/26/2004
• Est. Priority Date: 07/24/2000
• Status: Expired due to Term

• Current Assignee: Copperfield Licensing LLC (IP Edge LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Jin, Bo, Wong, Kaichiu
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/621,717
• Time in Patent Office: 1,555 Days
• Field of Search: 438/149, 438/404, 438/423, 438/424, 438/14, 438/691, 438/692
• US Class Current: 438/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

According to one embodiment, a structure for monitoring a process step may include an etch stop layer (102) formed on a substrate (104) and a trench emulation layer (106) formed over an etch stop layer (102). Monitor trenches (108) may be formed through a trench emulation layer (106) that terminate at an etch stop layer (102). Monitor trenches (108) may have a depth equal to a trench emulation layer (106) thickness. A trench emulation layer (106) thickness may be subject to less variation than a substrate trench depth. A monitor structure (100) may thus be used to monitor features formed by one or more process steps that may vary according to trench depth. Such process steps may include a shallow trench isolation insulator chemical mechanical polishing step. In addition, or alternatively, a monitor structure (100) may be formed on a non-semiconductor-on-insulator (SOI) wafer, but include SOI features, providing a less expensive alternative to monitoring some SOI process steps.

Claims

1. A method of forming a monitoring structure, comprising the step of:

depositing a first layer to a predetermined thickness equivalent to a desired trench depth;

etching the first layer to form monitor trenches that extend through the first layer and stop at an etch stop layer on a monitor wafer; and

forming a feature in, with, or in relation to the monitor trenches, wherein a process to be monitor with said monitoring structure forms a corresponding non-monitor trench in a different layer or material than the first layer, the feature varies according to a different trench depth.

2. The method of claim 1, further including:

forming the etch stop layer comprising silicon dioxide on a semiconductor substrate; and

depositing the first layer includes depositing a layer comprising polysilicon having a thickness less than 5000 angstroms.

3. The method of claim 1, further including:

the process to be monitored forms the non-monitor trench in a normal wafer; and

the monitor a is a non semiconductor-on-insulator (SOI) wafer and the normal wafer is a SOI wafer having semiconductor islands of a predetermined thickness; and

depositing the first layer of the predetermined thickness.

4. The method of claim 1, wherein:

etching the first layer includes forming a substrate trench etch mask on he first layer.

5. The method of claim 1, wherein:

etching the first layer includes forming a substrate trench etch mask pattern that essentially matches a semiconductor-on-insulator wafer lateral island isolation pattern.

6. The method of claim 1, wherein:

etching the first layer includes substantially anisotropically etching with a selectivity between the first layer and the etch stop layer of greater than 30;

1.

7. The method of claim 1, wherein:

forming a feature includes planarizing a trench insulator material that extends inside the monitor trenches.

8. The method of claim 7, wherein:

planarizing includes chemical-mechanical polishing the trench insulator material.

9. The method of claim 1, wherein:

forming a feature includes forming a feature selected from the group consisting of at least a portion of a semiconductor-on-insulator (SOI) transistor, SOI contact, and SOI interlayer dielectric.

10. A method of monitoring a semiconductor manufacturing process, comprising the steps of:

processing a monitor wafer having monitoring trenches formed in a first process layer of the monitoring wafer according to at least one process step that forms a feature, the feature being formed in a non-monitoring wafer in, with, or in relation to a different process layer than the first process layer in the semiconductor manufacturing process;

wherein

the first layer comprises a deposited layer and the different layer comprises a wafer substrate.

11. The method of claim 10, wherein:

the first layer comprises a deposited layer and the different layer comprises a semiconductor island layer formed as part of a semiconductor-on-insulator wafer substrate.

12. The method of claim 10, wherein:

the at least one process step includes depositing and planarizing a trench insulating material.

13. The method of claim 10, further including:

running th monitor wafer through the at least one process step with at least one normal wafer.

14. The method of claim 10, further including:

the feature include a trench insulator step height; and

examining the monitor structure in cross section to measure the insulator step height.

15. The method of claim 14, wherein:

the at least one process step include a shallow trench isolation (STI) insulator deposition step and a STI insulator chemical-mechanical polishing step.