Optical storage transfer performance

• US 6,810,443 B2
• Filed: 12/31/2002
• Issued: 10/26/2004
• Est. Priority Date: 12/31/2002
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Bennett, Joseph A.
• Primary Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US10/335,049
• Publication Number:
  US 20040128409A1
• Time in Patent Office: 665 Days
• Field of Search: 710/22, 710/33, 710/52, 711/100, 711/101
• US Class Current: 710/22
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0677 Optical disk device, e.g. CD-ROM, DVD

Abstract

One embodiment involves having a processor write a data transfer command to cacheable system memory. The processor then performs a write transaction to a deliver a “packet” command to an optical storage device. The optical storage device responds to the packet command by issuing an interrupt once the optical storage device has processed the packet command. The issuance of the interrupt indicates that the optical storage device is ready to receive a data transfer command. A host controller that is coupled to the optical storage device via a serial interconnect receives the interrupt. The host controller then causes a DMA transfer to occur which reads the data transfer command located in system memory and delivers the data transfer command to the optical storage device. The processor is not involved in servicing the interrupt and is therefore freed up to perform other tasks and overall system performance is improved.

Claims

1. An apparatus, comprising:

a storage device host controller to deliver a packet command received from a processor to an optical storage device over an interconnect, the storage device host controller to later receive an interrupt signal from the optical storage device; and

a direct memory access unit to retrieve a data transfer command from a system memory in response to the storage device host controller receiving the interrupt signal, the storage device host controller to then deliver the data transfer command to the optical storage device.

2. The apparatus of claim 1, wherein the interconnect is a serial interconnect.

3. The apparatus of claim 2, including a data transfer command base register to store a data transfer command address, the address indicating a location in system memory.

4. The apparatus of claim 3, the data transfer command including as many as 12 bytes of command information.

5. The apparatus of claim 4, wherein the interconnect is a serial ATA interconnect.

6. A system, comprising:

a processor;

a memory controller hub coupled to the processor;

a system memory coupled to the memory controller hub;

an optical storage device; and

a system logic device coupled to the memory controller hub and the system logic device coupled to the optical storage device via an interconnect, the system logic device including

a storage device host controller to deliver a packet command received from the processor to the optical storage device over an interconnect, the storage device host controller to later receive an interrupt signal from the optical storage device; and

a direct memory access unit to retrieve a data transfer command from the system memory in response to the storage device host controller receiving the interrupt signal, the storage device host controller to then deliver the data transfer command to the optical storage device.

7. The system of claim 6, wherein the interconnect is a serial interconnect.

8. The system of claim 7, including a data transfer command base register to store a data transfer command address, the address indicating a location in system memory.

9. The system of claim 8, the data transfer command including as many as 12 bytes of command information.

10. The system of claim 9, wherein the interconnect is a serial ATA interconnect.

11. A method, comprising:

storing a data transfer command in a system memory;

delivering a packet command to on optical storage device;

receiving an interrupt signal from the optical storage device at a storage device host controller; and

performing a direct memory access transaction to deliver the data transfer command from the system memory to the optical storage device.

12. The method of claim 11, wherein performing the direct memory access transaction includes retrieving the data transfer command from a location in the system memory indicated by the contents of a data transfer command base register.

13. The method of claim 12, further including a processor programming the data transfer command register with the location of the data transfer command in system memory.

14. The method of claim 13, wherein performing a direct memory access transaction includes the storage device host controller managing the direct memory access transaction.

15. The method of claim 14, wherein delivering a packet command to the optical storage device includes the processor initiating the delivering of the packet command to the optical storage device.