RAM functional test facilitation circuit with reduced scale

• US 6,810,498 B2
• Filed: 03/27/2002
• Issued: 10/26/2004
• Est. Priority Date: 04/25/2001
• Status: Expired due to Fees

• Current Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Shimizu, Ryuji
• Primary Examiner(s): Lamarre, Guy J.
• Assistant Examiner(s): Kerveros, James
• Application Number:
  US10/106,052
• Publication Number:
  US 20020162064A1
• Time in Patent Office: 944 Days
• Field of Search: 714/718, 714/724, 714/726, 714/727, 714/729, 365/201
• US Class Current: 714/726
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Abstract

The outputs of selectors 230 to 23N are respectively connected to the data inputs DI0 to DIN of a RAM 10A. One inputs of selectors 540 to 54N are respectively connected to the data outputs DO0 to DON of the RAM 10A, the other inputs are connected to corresponding outputs of the selectors 230 to 23N. The outputs of the selectors 540 to 54N are connected to data inputs D of respective scan flip-flops 520 to 52N. Not in a RAM test mode, data input lines 210 to 21N are selected by the selectors 230 to 23N to provide to the data inputs DI0 to DIN of the RAM 10A and to the scan flip-flops 520 to 52N through the selectors 540 to 54N, respectively.

Claims

1. A circuit for facilitating a functional test on a RAM, said RAM having a plurality of data inputs, address inputs and data outputs, comprising:

a plurality of first selectors each having first and second inputs and an output for selectively outputting a signal on said first or second input according to a mode signal, said first input thereof receiving a data signal in a normal mode, said outputs of said plurality of first selectors being connected to respective said data inputs of said RAM;

a first scan flip-flop having a data input, a scan in, a scan enable input, a data output and a scan out, said data output thereof being commonly connected to ones of said second inputs of said plurality of first selectors;

a plurality of second selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said mode signal, said first inputs of said plurality of second selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of second selectors being connected to respective said outputs of said plurality of first selectors; and

a plurality of second scan flip-flops each having a data input, a scan in, a scan enable input, a data output and a scan out, said data input thereof being connected to said respective outputs of said second selectors;

wherein said first scan flip-flop and said plurality of second scan flip-flops are cascaded with respect to said scan ins and scan outs thereof to constitute a scan register driven by a clock when a scan enable signal is active, said scan enable signal being provided to said scan enable inputs of said first scan flip-flop and said plurality of second scan flip-flops.

2. The circuit of claim 1, further comprising:

a plurality of third selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to a test mode signal, said first inputs of said plurality of third selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of third selectors being connected to respective said data outputs of said plurality of second scan flip-flops.

3. The circuit of claim 1, further comprising:

a third scan flip-flop having a data input, a scan in, a scan enable input receiving said scan enable signal, a data output and a scan out, said data output thereof being commonly connected to the remaining ones of said second inputs of said plurality of first selectors;

wherein said third scan flip-flop is connected with respect to said scan in and scan out thereof so as to constitute part of said scan register.

4. The circuit of claim 3, further comprising:

a plurality of fourth selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said test mode signal, said first input thereof receiving an address signal in said normal mode, said outputs of said plurality of fourth selectors being connected to respective said address inputs of said RAM;

a plurality of fifth scan flip-flops each having a data input, a scan in, a scan enable input receiving said scan enable signal, a data output and a scan out, said data inputs of said plurality of fifth scan flip-flops being connected to respective said outputs of said plurality of fourth selectors, said data outputs of said plurality of fifth scan flip-flops being connected to respective said second inputs of said plurality of fourth selectors;

wherein said plurality of fourth scan flip-flops are connected with respect to said scan ins and scan outs thereof so as to constitute part of said scan register.

5. The circuit of claim 1, wherein said RAM operates in synchronism with an internal clock signal, said circuit further comprising:

a first logic circuit ceasing said internal clock when said scan enable signal is active.

6. The circuit of claim 5, wherein said RAM further having a clock input and an inhibit input for ceasing said internal clock when said inhibit input is active,

wherein said first logic circuit has a first input receiving said scan enable signal, a second input receiving an inhibit signal, and an output connected to said inhibit input to be activated when said scan enable signal or said inhibit signal is active.

7. The circuit of claim 5, further comprising:

a second logic circuit ceasing a clock signal clocking said first and fourth scan flip-flops when said scan enable signal is active.

8. The circuit of claim 7, wherein said RAM further has a write enable input, said circuit further comprising:

a fifth selector having first and second inputs and an output for selectively outputting a signal on said first or second input according to said test mode signal, said output thereof being connected to said write enable input, said first input thereof receiving a write enable signal in said normal mode;

a fifth scan flip-flop having a data input, a scan in, a scan enable input receiving said scan enable signal, first and second data outputs complementary to each other, and a scan out, said first data output thereof being connected to said second input of said fifth selector;

a sixth selector having first and second inputs and an output for selectively outputting a signal on said first or second input according to selection control signal, said output thereof being connected to said data input of said fifth scan flip-flop, said first input thereof being connected to said output of said fifth selector, said second input thereof being connected to said second output of said fifth scan flip-flop;

wherein said fifth scan flip-flop is connected with respect to said scan in and scan out thereof so as to constitute part of said scan register.

9. The circuit of claim 8, further comprising:

a sixth scan flip-flop having a data input, a scan in, a scan enable input receiving said scan enable signal, first and second data outputs complementary to each other, and a scan out, said second data output thereof being connected to said data input thereof, either said first or second output thereof providing said selection control signal;

wherein said sixth scan flip-flop is connected with respect to said scan in and scan out thereof so as to constitute part of said scan register.

10. An integrated circuit devise comprising:

a circuit for facilitating a functional test on a RAM, said RAM having a plurality of data inputs, address inputs and data outputs, said circuit for facilitating comprising;

a plurality of first selectors each having first and second inputs and an output for selectively outputting a signal on said first or second input according to a mode signal, said first input thereof receiving a data signal in a normal mode, said outputs of said plurality of first selectors being connected to respective said data inputs of said RAM;

a first scan flip-flop having a data input, a scan in, a scan enable input, a data output and a scan out, said data output thereof being commonly connected to ones of said second inputs of said plurality of first selectors;

a plurality of second selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said mode signal, said first inputs of said plurality of second selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of second selectors being connected to respective said outputs of said plurality of first selectors; and

a plurality of second scan flip-flops each having a data input, a scan in, a scan enable input, a data output and a scan out, said data input thereof being connected to said respective outputs of said second selectors;

wherein said first scan flip-flop and said plurality of second scan flip-flops are cascaded with respect to said scan ins and scan outs thereof to constitute a scan register driven by a clock when a scan enable signal is active, said scan enable signal being provided to said scan enable inputs of said first scan flip-flop and said plurality of second scan flip-flops;

said integrated circuit devise further comprising;

another selector having first and second inputs and an output for selectively outputting a signal on said first or second input according to said test mode signal, said output thereof being connected to a scan in of said scan register; and

a logic circuit including a combinational circuit and another scan register having a scan out connected to said first input of said another selector;

wherein RAM test serial data is provided to said second input of said another selector without passing through said another scan register.

11. The integrated circuit devise of claim 10, further comprising:

a plurality of third selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to a test mode signal, said first inputs of said plurality of third selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of third selectors being connected to respective said data outputs of said plurality of second scan flip-flops.

12. The integrated circuit devise of claim 10, further comprising:

a third scan flip-flop having a data input, a scan in, a scan enable input receiving said scan enable signal, a data output and a scan out, said data output thereof being commonly connected to the remaining ones of said second inputs of said plurality of first selectors;

wherein said third scan flip-flop is connected with respect to said scan in and scan out thereof so as to constitute part of said scan register.

13. The integrated circuit devise of claim 12, further comprising:

a plurality of fourth selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said test mode signal, said first input thereof receiving an address signal in said normal mode, said outputs of said plurality of fourth selectors being connected to respective said address inputs of said RAM;

a plurality of fifth scan flip-flops each having a data input, a scan in, a scan enable input receiving said scan enable signal, a data output and a scan out, said data inputs of said plurality of fifth scan flip-flops being connected to respective said outputs of said plurality of fourth selectors, said data outputs of said plurality of fifth scan flip-flops being connected to respective said second inputs of said plurality of fourth selectors;

wherein said plurality of fourth scan flip-flops are connected with respect to said scan ins and scan outs thereof so as to constitute part of said scan register.

14. The integrated circuit devise of claim 10, wherein said RAM operates in synchronism with an internal clock signal, said circuit further comprising:

a first logic circuit ceasing said internal clock when said scan enable signal is active.

15. The integrated circuit devise of claim 14, wherein said RAM further having a clock input and an inhibit input for ceasing said internal clock when said inhibit input is active,

wherein said first logic circuit has a first input receiving said scan enable signal, a second input receiving an inhibit signal, and an output connected to said inhibit input to be activated when said scan enable signal or said inhibit signal is active.

16. The integrated circuit devise of claim 14, further comprising:

a second logic circuit ceasing a clock signal clocking said first and fourth scan flip-flops when said scan enable signal is active.

17. The integrated circuit devise of claim 16, wherein said RAM further has a write enable input, said circuit further comprising:

a fifth selector having first and second inputs and an output for selectively outputting a signal on said first or second input according to said test mode signal, said output thereof being connected to said write enable input, said first input thereof receiving a write enable signal in said normal mode;

a fifth scan flip-flop having a data input, a scan in, a scan enable input receiving said scan enable signal, first and second data outputs complementary to each other, and a scan out, said first data output thereof being connected to said second input of said fifth selector;

a sixth selector having first and second inputs and an output for selectively outputting a signal on said first or second input according to selection control signal, said output thereof being connected to said data input of said fifth scan flip-flop, said first input thereof being connected to said output of said fifth selector, said second input thereof being connected to said second output of said fifth scan flip-flop;

wherein said fifth scan flip-flop is connected with respect to said scan in and scan out thereof so as to constitute part of said scan register.

18. The integrated circuit devise of claim 17, further comprising:

a sixth scan flip-flop having a data input, a scan in, a scan enable input receiving said scan enable signal, first and second data outputs complementary to each other, and a scan out, said second data output thereof being connected to said data input thereof, either said first or second output thereof providing said selection control signal;

wherein said sixth scan flip-flop is connected with respect to said scan in and scan out thereof so as to constitute part of said scan register.