Surge protection circuit for semiconductor devices

• US 6,812,528 B2
• Filed: 06/06/2001
• Issued: 11/02/2004
• Est. Priority Date: 06/07/2000
• Status: Expired due to Term

• Current Assignee: Vista Peak Ventures LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: NEC Corporation
• Inventors: Uchida, Hiroyuki
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/874,296
• Publication Number:
  US 20010050835A1
• Time in Patent Office: 1,245 Days
• Field of Search: 257/347, 257/355, 257/356, 257/357
• US Class Current: 257/355
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A surge protection device includes a gate electrode embedded in an insulator, a source electrode and a drain electrode on the insulator. The source and drain electrodes respectively form first and second capacitances with the gate electrode. A semiconductor island is provided on the insulator to form a channel between the source and drain electrodes and a third capacitance with the gate electrode. The third capacitance is smaller than either of the first and second capacitances. The source and drain electrodes are adapted for connection to external circuitry for establishing a low-impedance path when the external circuitry is subjected to a surge potential.

Claims

1. A surge protection device, comprising:

an insulator;

a gate electrode embedded in said insulator;

a source electrode and a drain electrode on said insulator, said source and drain electrodes respectively forming first and second capacitances with said gate electrode; and

a semiconductor island on said insulator, said island forming a channel region between said source and drain electrodes and forming a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances,

said source and drain electrodes being adapted for connection to external circuitry for establishing a low-impedance path when the external circuitry is subjected to a surge potential.

2. The surge protection device of claim 1, wherein said first and second capacitances are of equal value.

3. A surge protection circuit, comprising:

a plurality of surge protection devices, each of said protection devices comprising;

an insulator;

a gate electrode embedded in said insulator;

a source electrode and a drain electrode on said insulator, said source and drain electrodes respectively forming first and second capacitances with said gate electrode; and

a semiconductor island on said insulator, said island forming a channel region between said source and drain electrodes and forming a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances,

said source and drain electrodes of each of said surge protection devices being respectively connected to the drain and source electrodes of adjacent ones of said plurality of surge protection devices and adapted to be connected to pad electrodes of external circuitry for establishing connections with said adjacent surge protection devices when one of the pad electrodes is subjected to a surge potential.

4. The surge protection circuit of claim 3, wherein said first and second capacitances of each of said surge protection devices are of equal value.

5. The surge protection circuit of claim 3, further comprising:

a second plurality of surge protection devices identical in structure to said plurality of surge protection devices,

the source-drain paths of said second plurality of surge protection devices being respectively connected to the pad electrodes via respective lines for establishing a low-impedance path to ground.

6. The surge protection circuit of claim 3, further comprising:

a first additional surge protection device identical in structure to said plurality of surge protection devices and connected between a first one of said plurality of surge protection devices and ground; and

a second additional surge protection device identical in structure to said plurality of surge protection devices and connected between a second one of said plurality of surge protection devices and ground.

7. The surge protection circuit of claim 6, further comprising a second plurality of surge protection devices identical in structure to said plurality of surge protection devices, the source-drain paths of said second plurality of surge protection devices being respectively connected to the pad electrodes via respective lines for establishing a low-impedance path to ground.

8. A surge protection circuit, comprising:

a plurality of surge protection devices, each of said protection devices comprising;

an insulator;

a gate electrode embedded in said insulator;

a source electrode and a drain electrode on said insulator, said source and drain electrodes respectively forming first and second capacitances with said gate electrode; and

a semiconductor island on said insulator, said island forming a channel region between said source and drain electrodes and forming a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances,

said source and drain electrodes of each of said surge protection devices being adapted to be connected in series to external circuitry for establishing a low-impedance path to ground when the external circuitry is subjected to a surge potential.

9. The surge protection circuit of claim 8, wherein said first and second capacitances of each of said surge protection devices are of equal value.

10. A surge protection circuit for a semiconductor display panel, said circuit comprising:

a first plurality of pad electrodes;

a plurality of vertical signal lines connected respectively to said first plurality of pad electrodes;

a second plurality of pad electrodes;

a plurality of horizontal signal lines intersecting said vertical signal lines, said horizontal signal lines being connected respectively to said second plurality of pad electrodes; and

a plurality of floating-gate field effect transistors, each having a channel capacitance and including a floating gate electrode, a source electrode and a drain electrode, said source and drain electrodes of each of said transistors being respectively connected to the drain and source electrodes of adjacent ones of said plurality of floating-gate transistors and further connected to respective ones of said first plurality of pad electrodes, each of said transistors being responsive to the respective pad electrode, or to the vertical signal line connected to the respective pad electrode, being subjected to a surge potential for developing a voltage on said channel capacitance sufficient to turn on said floating-gate field effect transistor and establish connections with said adjacent floating-gate transistors.

13. The surge protection circuit of claim 10, further comprising a second plurality of floating-gate transistors, said source-drain paths of said second plurality of floating-gate transistors being respectively connected to said first plurality of pad electrodes via respective lines for establishing a low-impedance path to ground.

14. The surge protection circuit of claim 10, further comprising:

a first additional floating-gate transistor connected between a first one of said plurality of floating-gate transistors and ground; and

a second additional floating-gate transistor connected between a second one of said plurality of floating-gate transistors and ground.

15. The surge protection circuit of claim 14, further comprising a second plurality of floating-gate transistors, the source-drain paths of said second plurality of floating-gate transistors being respectively connected to said first plurality of pad electrodes via said vertical signal lines for establishing a low-impedance path to ground.

11. A surge protection circuit for a semiconductor display panel, said circuit comprising:

a first plurality of pad electrodes;

a plurality of vertical signal lines connected respectively to said first plurality of pad electrodes;

a second plurality of pad electrodes;

a plurality of horizontal signal lines intersecting said vertical signal lines, the horizontal signal lines being connected respectively to said second plurality of pad electrodes; and

a plurality of floating-gate field effect transistors, each including an insulator, a floating gate electrode, a source electrode and a drain electrode, said source and drain electrodes of each of said transistors being respectively connected to the drain and source electrodes of adjacent ones of said plurality of floating-gate transistors and further connected to respective ones of said first plurality of pad electrodes for establishing connections with said adjacent floating-gate transistors when the respective pad electrode, or the vertical signal line connected to the respective pad electrode, is subjected to a surge potential,

wherein in each transistor said floating gate electrode is embedded in said insulator, said source electrode and said drain electrode are formed on said insulator so that said source and drain electrodes respectively form first and second capacitances with said floating gate electrode, and a semiconductor island is provided on said insulator to form a channel between said source and drain electrodes and to form a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances.

12. The surge protection circuit of claim 11 wherein said first and second capacitances of each of said floating-gate transistors are of equal value.

16. A surge protection circuit for a semiconductor display panel, comprising:

a first plurality of pad electrodes;

a plurality of vertical signal lines connected respectively to said first plurality of pad electrodes;

a second plurality of pad electrodes;

a plurality of horizontal signal lines intersecting said vertical signal lines, the horizontal signal lines being connected respectively to said second plurality of pad electrodes, and

a plurality of floating-gate field effect transistors, each having a channel capacitance and including a floating gate electrode, a source electrode and a drain electrode, said source and drain electrodes of each of said transistors being respectively connected to said vertical signal lines, each of said transistors being responsive to the respective vertical signal line, or the pad electrode connected to the respective vertical signal line, being subjected to a surge potential for developing a voltage on said channel capacitance sufficient to turn on said floating-gate field effect transistor and establish a low-impedance path to ground.

17. A surge protection circuit for a semiconductor display panel, said circuit comprising:

a first plurality of pad electrodes;

a plurality of vertical signal lines connected respectively to said first plurality of pad electrodes;

a second plurality of pad electrodes;

a plurality of horizontal signal lines intersecting said vertical signal lines, the horizontal signal lines being connected respectively to said second plurality of pad electrodes, and

a plurality of floating-gate field effect transistors, each including an insulator, a floating gate electrode, a source electrode and a drain electrode, said source and drain electrodes of each of said transistors being respectively connected to said vertical signal lines for establishing a low-impedance path to around when the respective vertical signal line, or the pad electrode connected to the respective vertical signal line, is subjected to a surge potential,

wherein in each transistor said floating gate electrode is embedded in said insulators, and said source electrode and said drain electrode are formed on said insulator so that said source and drain electrodes respectively form first and second capacitances with said floating gate electrode, and a semiconductor island is provided on said insulator to form a channel between said source and drain electrodes and to form a third capacitance with said gate electrode, the third capacitance being smaller than either of said first and second capacitances.

18. The surge protection circuit of claim 17, wherein said first and second capacitances of each of said floating-gate transistors are of equal value.

19. A surge protection device, comprising:

a gate electrode;

a source electrode forming a first capacitance with said gate electrode;

a drain electrode forming a second capacitance with said gate electrode; and

a channel region between said source and drain electrodes and forming a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances,

said source and drain electrodes being adapted for connection to external circuitry for establishing a low-impedance path when the external circuitry is subjected to a surge potential.

20. A surge protection circuit, comprising:

a plurality of surge protection devices, each of said protection devices comprising;

a gate electrode;

a source electrode forming a first capacitance with said gate electrode;

a drain electrode forming a second capacitance with said gate electrode; and

a channel region between said source and drain electrodes and forming a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances,

said source and drain electrodes of each of said surge protection devices being respectively connected to the drain and source electrodes of adjacent ones of said plurality of surge protection devices and adapted to be connected to pad electrodes of external circuitry for establishing connections with said adjacent surge protection devices when one of the pad electrodes is subjected to a surge potential.

21. A surge protection circuit, comprising:

a plurality of surge protection devices, each of said protection devices comprising;

a gate electrode;

a source electrode forming a first capacitance with said gate electrode;

a drain electrode forming a second capacitance with said gate electrode; and

a semiconductor island forming a channel region between said source and drain electrodes and forming a third capacitance with said gate electrode, said third capacitance being smaller than either of said first and second capacitances,

said source and drain electrodes of each of said surge protection devices being adapted to be connected in series to external circuitry for establishing a low-impedance path to ground when the external circuitry is subjected to a surge potential.

22. A surge protection circuit for a semiconductor display panel, said circuit comprising:

a plurality of vertical signal lines;

a plurality of horizontal signal lines intersecting said vertical signal lines; and

a plurality of floating-gate field effect transistors, each having a channel capacitance and including a floating gate electrode, a source electrode and a drain electrode, said source and drain electrodes of each of said transistors being respectively connected to the drain and source electrodes of adjacent ones of said plurality of floating-gate transistors and adapted to be connected to respective pad electrodes so as to be responsive to the respective pad electrode being subjected to a surge potential for developing a voltage on said channel capacitance sufficient to turn on said floating-gate field effect transistor and establish connections with said adjacent floating-gate transistors.

23. A surge protection circuit for a semiconductor display panel, comprising:

a plurality of vertical signal lines;

a plurality of horizontal signal lines intersecting said vertical signal lines; and

a plurality of floating-gate field effect transistors, each having a channel capacitance and including a floating gate electrode, a source electrode and a drain electrode, said source and drain electrodes of each of said transistors being respectively connected to said vertical signal lines, each of said transistors being responsive to the respective vertical signal line being subjected to a surge potential for developing a voltage on said channel capacitance sufficient to turn on said floating-gate field effect transistor and establish a low-impedance path to ground.