Communications architecture for a high throughput storage processor employing extensive I/O parallelization
First Claim
1. A storage processor for a RAID system, comprising:
- a communications device connecting at least a front end (FE) connectable to a requesting device, a back end (BE) connectable to a disk array, and a control processor and control memory;
said communications device connecting a user memory, a DMA engine, a data translator, and a crossbar switch;
at least one data channel including at least one buffer;
said control processor initiating a process on target data transmitted, on a target data channel defined by said communications device, to said control memory by said requesting device and in response to a command from said requesting device and an interrupt invoked by said requesting device;
said communications device being configured such that said control processor does not respond to said interrupt until all of said target data is received in said user memory.
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Accused Products
Abstract
A storage processor for a block storage RAID array services disk storage block requests from one or more hosts. At its heart, a application specific integrated chip (ASIC) supports a store and forward data transfer regime in that host to disk transfers are made by placing data in storage processor memory under control of the storage processor, operated on by the ASIC, and sent to the disk array. Efficient handling of ordering is, preferably, provided by hardware logic-based masking of interrupts and by other mechanisms. Embodiments help to insure that shared data paths are flushed of non-critical data quickly to sustain more critical data, for example, that required to sustain high throughput.
71 Citations
25 Claims
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1. A storage processor for a RAID system, comprising:
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a communications device connecting at least a front end (FE) connectable to a requesting device, a back end (BE) connectable to a disk array, and a control processor and control memory;
said communications device connecting a user memory, a DMA engine, a data translator, and a crossbar switch;
at least one data channel including at least one buffer;
said control processor initiating a process on target data transmitted, on a target data channel defined by said communications device, to said control memory by said requesting device and in response to a command from said requesting device and an interrupt invoked by said requesting device;
said communications device being configured such that said control processor does not respond to said interrupt until all of said target data is received in said user memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 16, 17, 18)
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10. A storage processor for a RAID system, comprising:
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a communications device connecting at least a front end (FE) connectable to a requesting device, a back end (BE) connectable to a disk array, and a control processor and control memory;
said communications device connecting a user memory, a DMA engine, a data translator, and a crossbar switch;
at least one data channel including at least one buffer;
said control processor initiating a process by said DMA engine, on target data transmitted on a target data channel defined by said communications device, said process requiring that said target data channel be flushed of said target data;
said control processor initiating said process responsively to an interrupt invoked by said requesting device;
said communications device being configured to mask said interrupt until said target data is flushed from said target data channel. - View Dependent Claims (11, 12, 13, 14, 15)
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19. A method of ordering parallel I/O in a storage processor, comprising the steps of:
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generating a target data transfer request;
posting target data on a target channel;
generating an interrupt applied to a controller to initiate an operation responsive to said target data;
masking said interrupt responsively to said target data being flushed from said target channel;
unmasking said interrupt responsively to said target data being cleared from said target channel. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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Specification