Readout of array-based analog data in semiconductor-based devices

• US 6,819,280 B2
• Filed: 11/12/2003
• Issued: 11/16/2004
• Est. Priority Date: 03/30/2001
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Huang, Steve, Ang, Lin Ping
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): Lauture, Joseph
• Application Number:
  US10/704,824
• Publication Number:
  US 20040095490A1
• Time in Patent Office: 370 Days
• Field of Search: 341/162, 341/155, 358/482, 358/463
• US Class Current: 341/162
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

Systems and techniques to readout array-based analog data with reduced power requirements and reduced fixed pattern noise. An image sensor on an integrated circuit may include a sensor array to provide array-based analog data, a parallel sampling circuitry to receive the array-based analog data in parallel, a pipelined amplification circuitry to serially amplify the received array-based analog data, and an analog-to-digital converter to convert the amplified array-based analog data into digital data.

Claims

1. An image sensor comprising:

an image sensor array;

parallel sampling circuitry coupled with the image sensor array; and

a serial readout circuitry coupled with the parallel sampling circuitry, the serial readout circuitry including a gain stage and an analog-to-digital converter;

wherein the parallel sampling circuitry comprises parallel sample and hold and charge mode readout circuitry not including an amplifier and configured to sample the image sensor array using correlated double sampling.

2. The image sensor of claim 1, wherein the analog-to-digital converter comprises a differential error-correcting analog-to-digital converter.

3. The image sensor of claim 1, wherein the image sensor array comprises an active pixel sensor array including at least one photodiode.

4. The image sensor of claim 1, wherein the gain stage comprises a pipelined gain stage.

5. The image sensor of claim 4, wherein the pipelined gain stage comprises three gain stages.

6. The image sensor of claim 1, further comprising a control circuitry to perform digital processing operations on digital data received from the analog-to-digital converter.

7. The image sensor of claim 6, wherein the digital processing operations comprise black level calibration and correction.

8. An image sensor, comprising:

an image sensor array;

parallel sampling circuitry coupled with the image sensor array; and

a serial readout circuitry coupled with the parallel sampling circuitry, the serial readout circuitry including a gain stage and an analog-to-digital converter;

wherein the gain stage comprises a differential switched capacitor circuitry including at least two programmable capacitors to amplify signal and reset values passed from sequential portions of the parallel sampling circuitry.

9. An image sensor comprising:

array means for converting received photons into electrical signals;

low fixed-pattern-noise means for sampling the electrical signals; and

serial means for amplifying the sampled electrical signals separate from said parallel means;

wherein said low fixed-pattern-noise means comprises column parallel correlated double sampling means for sampling signal and reset values from the array means without amplification.

10. The image sensor of claim 9, wherein said array means comprises an active pixel sensor array.

11. The image sensor of claim 9, wherein said serial means comprises gain-stage means for low-power amplification of the electrical signals and means for converting amplified electrical signals into digital data.