API communications for vertex and pixel shaders
First Claim
1. A method for communicating between a 3-D graphics API of a host computing system having a main memory stack and a 3-D graphics hardware rendering device having on-chip register storage, comprising:
- receiving at least one instruction having at least one graphics data argument by the 3-D API;
formatting said at least one instruction for the register storage of the hardware rendering device;
providing said at least one formatted instruction to the hardware rendering device;
processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware rendering device without accessing the main memory stack of the host computing system;
outputting the result of said processed at least one graphics data argument from said hardware rendering device in accordance with said at least one formatted instruction;
wherein said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the hardware rendering device the fractional portion of said at least one floating point number; and
wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments.
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Accused Products
Abstract
A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.
83 Citations
44 Claims
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1. A method for communicating between a 3-D graphics API of a host computing system having a main memory stack and a 3-D graphics hardware rendering device having on-chip register storage, comprising:
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receiving at least one instruction having at least one graphics data argument by the 3-D API;
formatting said at least one instruction for the register storage of the hardware rendering device;
providing said at least one formatted instruction to the hardware rendering device;
processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware rendering device without accessing the main memory stack of the host computing system;
outputting the result of said processed at least one graphics data argument from said hardware rendering device in accordance with said at least one formatted instruction;
wherein said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the hardware rendering device the fractional portion of said at least one floating point number; and
wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A computer system, comprising:
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a hardware rendering device having on-chip register storage;
a host computing system having a main memory and having stored thereon a 3-D API for communicating at least one instruction having at least one graphics data argument formatted for the register storage of said hardware rendering device to said hardware rendering device;
wherein said hardware rendering device receives said at least one instruction;
wherein the hardware rendering device processes said at least one graphics data argument incident to the performance of said at least one instruction without accessing the main memory of the host computing system and said hardware rendering device outputs the result of the processing;
wherein said at least one instruction is an instruction with at least one floating point number argument and said hardware rendering device outputs the fractional portion of said at least one floating point number; and
wherein said hardware rendering device outputs four fractional portions of corresponding four floating point number arguments. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for communicating between a 3-D graphics API of a host computing system having a main memory stack and a hardware procedural shader having on-chip register storage, comprising:
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receiving at least one instruction having at least one graphics data argument by the 3-D API;
formatting said at least one instruction for use with the hardware procedural shader;
providing said at least one formatted instruction to said hardware procedural shader;
processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware procedural shader without accessing the main memory stack of the host computing system;
outputting the result of said processed at least one graphics data argument from said hardware procedural shader in accordance with said at least one formatted instruction;
wherein the method is a method for communicating between a 3-D graphics API of a host computing system and a hardware vertex shader with on-chip register storage, and said at least one instruction is an instruction with at least one floating point number argument and said outputting includes outputting from the vertex shader the fractional portion of said at least one floating point number; and
wherein said outputting includes outputting four fractional portions of corresponding four floating point number arguments. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A computer system, comprising:
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a hardware procedural shader having on-chip register storage;
a host computing system having a main memory having stored thereon a 3-D API for communicating at least one instruction having at least one graphics data argument formatted for said hardware procedural shader to said hardware procedural shader;
wherein said hardware procedural shader receives said at least one instruction;
wherein the hardware procedural shader processes said at least one graphics data argument incident to the performance of said at least one instruction without accessing the main memory of the host computing system and said hardware procedural shader outputs the result of the processing;
wherein said hardware procedural shader is a vertex shader, and said at least one instruction is an instruction with at least one floating point number argument and said vertex shader outputs the fractional portion of said at least one floating point number; and
wherein said vertex shader outputs four fractional portions of corresponding four floating point number arguments. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44)
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Specification