System and circuitry for measuring echoes on subscriber loops

• US 6,819,744 B1
• Filed: 09/29/2000
• Issued: 11/16/2004
• Est. Priority Date: 09/30/1999
• Status: Active Grant

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Telcordia Technologies Incorporated (Telefonaktiebolaget LM Ericsson)
• Inventors: Banwell, Thomas C., Galli, Stefano
• Primary Examiner(s): TRAN, QUOC DUC
• Application Number:
  US09/676,740
• Time in Patent Office: 1,509 Days
• Field of Search: 379/1.01, 379/1.03, 379/1.04, 379/3, 379/9.06, 379/14.01, 379/10.01, 379/10.02, 379/15.01, 379/21, 379/22, 379/22.01, 379/22.02, 379/22.03, 379/22.06, 379/22.07, 379/24, 379/26.01, 379/26.02, 379/27.01, 379/27.03, 379/29.01, 379/29.02, 379/29.03, 379/29.04, 379/29.05, 379/29.1, 324/500, 324/512, 324/523, 324/526, 324/527, 324/532, 324/533, 324/534
• US Class Current: 379/1.01
• CPC Class Codes: H04B 3/493 Testing echo effects or singing
• CPC Class Codes: H04M 3/002 Applications of echo suppressors or cancellers in telephonic connections in two-way loud-speaking telephone systems H04M9/08, echo suppressors or cancellers per se H04B3/20
• CPC Class Codes: H04M 3/30 for subscriber's lines , for the local loop

Abstract

A system for performing broadband differential time domain measurement on a subscriber loop. The system comprises a waveform generator coupled to a sampling head. The sampling head includes positive and negative pulse generators each coupled to one of the lines of the subscriber loop. The subscriber lines are in turn also coupled to two inputs of a differential amplifier, whose output is connected to an oscilloscope or other detector.

Claims

1. A system for performing broadband differential time domain measurement on a subscriber loop having access terminals, said system comprising:

a waveform generator having an output;

a detector having an input; and

a DC coupled sampling head comprising

a buffer amplifier having an input and first and second outputs, said buffer amplifier input coupled to said waveform generator output;

a positive pulse generator coupled to said buffer amplifier first output and to one of said loop access terminals, said positive pulse generator comprising an inverter in series with a resistor, said positive pulse generator being coupled to said buffer amplifier first output, and said positive pulse generator resistor coupled to one of said access terminals;

a negative pulse generator coupled to said buffer amplifier second output and to the other of said loop access terminals; and

a difference amplifier having an output and first and second inputs, said difference amplifier first input coupled to said one of said loop access terminals, said difference amplifier second input coupled to said other of said loop access terminals, and said difference amplifier output coupled to said detector input.

2. The system of claim 1 wherein said buffer amplifier comprises a first inverter coupled to said buffer amplifier input and said buffer amplifier first output, a second inverter coupled to said buffer amplifier second output, and means for level translation coupled to said second inverter and a resistor, said resistor being coupled in series to said first inverter and buffer amplifier first output.

3. The system of claim 1 wherein said negative pulse generator comprises an inverter in series with a resistor, said negative pulse inverter being coupled to said buffer amplifier second output, and said positive pulse generator resistor coupled to one of said access terminals.

4. The system of claim 3 wherein said negative pulse generator inverter and said positive pulse generator inverter each comprises an individual inverter having an output that is coupled to the appropriate loop access terminal through a series resistor so as to effect equal current sharing among said inverters.

5. The system of claim 4 wherein said inverters comprise high-speed CMOS inverters.

6. The system of claim 5 wherein said waveform generators are each a pulse generator.

7. The system of claim 4 further comprising means for displaying a measurement result.

8. The system of claim 7 wherein said means for displaying and said detector are coupled together in an oscilloscope.

9. The system of claim 7 further comprising a processor having a process for identifying loop make up, said processor being coupled to said waveform, generator and said detector and said processor tangibly embodying a program, said program comprising the steps of:

transmitting at least one probing pulse onto the loop from the pulse generator,

acquiring data based on said at least one transmitted pulse, said received echoes being caused by discontinuities on the loop;

identifying the gauge of a first loop section of the loop based on said acquired data;

calculating a slowly decaying signal based on said identified gauge;

subtracting said slowly decaying signal from said acquired data to produce compensated data, said compensated data having echo signals which represent discontinuities on the loop; and

determining the loop make-up based on said compensated data.

10. A sampling head for performing broadband differential time domain measurement on a subscriber loop having first and a second access terminal, said sampling head comprising:

a buffer amplifier having an input and first and second outputs;

a positive pulse generator coupled to said buffer amplifier first output, said positive pulse generator comprising an inverter in series with a resistor, said positive pulse generator inverter being coupled to said buffer amplifier first output;

a negative pulse generator coupled to said buffer amplifier second output; and

a difference amplifier having an output and first and second inputs, said difference amplifier first input coupled to said buffer amplifier first output, said difference amplifier second input coupled to said buffer amplifier second output.

11. The sampling head of claim 10 wherein said buffer amplifier comprises a first inverter coupled to said buffer amplifier input and said buffer amplifier first output, a second inverter coupled to said buffer amplifier second output, and means for level translation coupled to said second inverter and a resistor, sad resistor coupled in series to said first inverter and buffer amplifier first output.

12. The sampling head of claim 10 wherein said negative pulse generator comprises an inverter in series with a resistor, said negative pulse generator inverter being coupled to said buffer amplifier second output.

13. The sampling head of claim 12 wherein said negative pulse generator and said positive pulse generator each comprises an individual inverter having an output that is coupled to the appropriate loop access terminal through a series resistor so as to effect equal current sharing among said inverters.

14. The sampling head of claim 13 wherein said buffer amplifier is coupled to a pulse generator, said difference amplifier first and second outputs are connected to the first and second access terminals, respectively, and said difference amplifier output is connected to an oscilloscope.

15. A sampling head for performing broadband differential time domain measurement on a subscriber loop having first and second access terminals, said sampling head comprising:

a buffer amplifier having an input and first and second outputs;

a positive pulse generator including an inverter coupled to said buffer amplifier first output;

a negative pulse generator including an inverter coupled to said buffer amplifier second output; and

a difference amplifier having an output and first and second inputs, said difference amplifier first input coupled to said buffer amplifier first output and said difference amplifier second input coupled to said buffer amplifier second output.