Background-calibrating pipelined analog-to-digital converter

• US 6,822,601 B1
• Filed: 07/23/2003
• Issued: 11/23/2004
• Est. Priority Date: 07/23/2003
• Status: Expired due to Fees

• Current Assignee: Jieh-Tsorng Wu, Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Original Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Inventors: Lee, Zwei-Mei, Liu, Hung-Chih, Wu, Jieh-Tsomg
• Primary Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US10/604,458
• Time in Patent Office: 489 Days
• Field of Search: 341/155, 341/161, 341/118, 341/120, 341/150
• US Class Current: 341/161
• CPC Class Codes: H03M 1/1004 without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated H03M1/1009, H03M1/1071 take precedence
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence

Abstract

A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

Claims

1. A multiplying digital-to-analog converter (MDAC) stage for a pipelined analog-to-digital converter, the MDAC stage comprising:

an input node for receiving an analog signal;

a sub-analog-to-digital converter for converting the analog signal to a digital code;

an amplifier;

a first capacitance selectively connected between the input node and the amplifier input and between the amplifier input and the amplifier output; and

a plurality of second capacitances in parallel selectively connected between the input node and the amplifier input and between a corresponding plurality of digital reference signals and the amplifier input, the plurality of digital reference signals comprising digital signals corresponding to the digital code and a first calibration signal;

wherein during a sample phase the first capacitance is connected, between the input node and the amplifier input and the plurality of second capacitances are connected in parallel between the input node and the amplifier input, and during a hold phase the first capacitance is connected between the amplifier input and the amplifier output and the plurality of second capacitances am connected in parallel between the plurality of digital reference signals and the amplifier input.

2. The MDAC stage of claim 1 wherein the sum of the plurality of second capacitances is nominally equal to the first capacitance.

3. A pipelined analog-to-digital converter comprising a series of MDAC stages of claim 1.

4. The piplined analog-to-digital converter of claim 3 further comprising:

a multiplier connected to the output of the last MDAC stage of the series, thc multiplier for determining a product of the last MDAC stage output and a second calibration signal corresponding to the first calibration signal;

a low-pass filter connected to the multiplier for filtering output of the multiplier and outputting a DC component, and

an encoder for receiving output of the MDAC stages and generating a digital output signal, and for compensating the digital output signal with the DC component.

5. The pipelined analog-to-digital converter of claim 4 wherein the first and second calibration signals are random digital binary valued sequences having the same waveform shape.

6. The pipelined analog-to-digital converter of claim 4 further comprising a pseudo-random signal generator for generating the first and second calibration signals.

7. The pipelined analog-to-digital converter of claim 4 further comprising a memory for storing the DC component, the memory accessible by the encoder.

8. A method for background calibrating a pipelined analog-to-digital converter comprising a series of multiplying digital-to-analog converter (MDAC) stages, the method comprising:

sampling an input analog signal on a first capacitance and a plurality of second capacitances of an MDAC stage during a sample phase;

applying a first calibration signal to a second capacitance of the MDAC stage during a hold phase;

combining output of the last MDAC stage of the series with a second calibration signal corresponding to the first calibration signal; and

filtering the second calibration signal from the digital output of the pipelined analog-to-digital converter.

9. The method of claim 8 further comprising sequentially applying the first calibration signal to second capacitances of all MDAC stages during corresponding hold phases, said sequential application being in order of increasing significant bit values of the MDAC stages.

10. The method of claim 8 wherein the sum of the plurality of second capacitances is nominally equal to the first capacitance.

11. The method of claim 8 where the first and second calibration signals are random digital binary-valued sequences having the same waveform shape.